2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA) (2000)
Jan. 8, 2000 to Jan. 12, 2000
Sally A. McKee , University of Utah
Al Davis , University of Utah
Binu K. Mathew , University of Utah
John B. Carter , University of Utah
We are attacking the memory bottleneck by building a "smart" memory controller that improves effective memory bandwidth, bus utilization, and cache efficiency by letting applications dictate how their data is accessed and cached. This paper describes a Parallel Vector Access unit (PVA), the vector memory subsystem that efficiently "gathers" sparse, strided data structures in parallel on a multi-bank SDRAM memory. We have validated our PVA design via gate-level simulation, and have evaluated its performance via functional simulation and formal analysis. On unit-stride vectors, PVA performance equals or exceeds that of an SDRAM system optimized for cache line fills. On vectors with larger strides, the PVA is up to 32.8 times faster. Our design is up to 3.3 times faster than a pipelined, serial SDRAM memory system that gathers sparse vector data, and the gathering mechanism is two to five times faster than in other PVAs with similar goals. Our PVA only slightly in-creases hardware complexity with respect to these other systems, and the scalable design is appropriate for a range of computing platforms, from vector supercomputers to commodity PCs.
Sally A. McKee, Al Davis, Binu K. Mathew, John B. Carter, "Design of a Parallel Vector Access Unit for SDRAM Memory Systems", 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA), vol. 00, no. , pp. 39, 2000, doi:10.1109/HPCA.2000.824337