2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA) (2000)
Jan. 8, 2000 to Jan. 12, 2000
Anthony-Trung Nguyen , University of Illinois at Urbana-Champaign
Liuxi Yang , Sun Microsystems
Josep Torrellas , University of Illinois at Urbana-Champaign
Dramatic increases in the number of transistors that can be integrated on a VLSI chip will soon allow commodity microprocessors to include both processor and a sizable fraction of main memory on chip. Distributed Shared-Memory (DSM) multiprocessors typically use the latest off-the-shelf microprocessors and thus will be affected by the upcoming processor-memory integration. In this paper, we explore how a cache-coherent DSM machine built around Processor-In-Memory (PIM) chips might be cost-effectively organized.To take advantage of the close coupling between processor and memory, we propose tagging the memory and organizing it as a cache. Furthermore, commercial considerations dictate the use of off-the-shelf hardware largely designed for uniprocessors. Consequently, we keep the directory control off-chip. To keep the multiprocessor cheap and simple, and to allow for reconfigurability, directory control is performed by chips that are identical to the ones used as compute nodes. As a result, the machine hardware can be easily reconfigured for computing or coherence-handling depending on the needs of the application. We also propose a cache coherence protocol that is tailored to our architecture: it uses the memory very efficiently while exploiting the large caching space available. Overall, the resulting machine is simple and inexpensive, and delivers performance that is comparable to, and higher than, the more expensive traditional COMA and CC-NUMA organizations, respectively.
DSM, processor-in-memory, NUMA, COMA, multiprocessor, coherence protocol, directory controller, reconfigurable, PIM
Anthony-Trung Nguyen, Liuxi Yang, Josep Torrellas, "Toward A Cost-Effective DSM Organization that Exploits Processor-Memory Integration", 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA), vol. 00, no. , pp. 15, 2000, doi:10.1109/HPCA.2000.824335