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Proceedings Fifth International Symposium on High-Performance Computer Architecture (1999)
Orlando, Florida
Jan. 9, 1999 to Jan. 12, 1999
ISBN: 0-7695-0004-8

Preface (PDF)

pp. ix

List of Referees (PDF)

pp. xii
Session 1: Performance Enhancements
Session 2: Simultaneous Multithreading

The Synergy of Multithreading and Access/Execute Decoupling (Abstract)

Joan-Manuel Parcerisa , Universitat Polit?cnica de Catalunya - Barcelona
Antonio González , Universitat Polit?cnica de Catalunya - Barcelona
pp. 59
Session 3: Memory Systems
Session 4: Instruction Scheduling & Speculation
Session 5A: Cache Coherence
Session 5B: SMP Clusters

WildFire: A Scalable Path for SMPs (Abstract)

Erik Hagersten , Sun Microsystems, Inc.
Michael Koster , Sun Microsystems, Inc.
pp. 172
Session 6A: Cache and I/O Systems

RAPID-Cache ? A Reliable and Inexpensive Write Cache for Disk I/O Systems (Abstract)

Yiming Hu , University of Rhode Island
Qing Yang , University of Rhode Island
Tycho Nightingale , University of Rhode Island
pp. 204
Session 6B: Communication Issues I
Session 7A: Shared Memory

MP-LOCKs: Replacing H/W Synchronization Primitives with Message Passing (Abstract)

Chen-Chi Kuo , University of Utah
John Carter , University of Utah
Ravindra Kuramkote , University of Utah
pp. 284
Session 7B: Communication Issues II

Communication Studies of Single-Threaded and Multithreaded Distributed-Memory Machines (A Short Summary) (Abstract)

Andrew Sohn , New Jersey Institute of Technology
Yunheung Paek , New Jersey Institute of Technology
Jui-Yuan Ku , New Jersey Institute of Technology
Yuetsu Kodama , Electrotechnical Laboratory
Yoshinori Yamaguchi , Electrotechnical Laboratory
pp. 310

Impact of Buffer Size on the Efficiency of Deadlock Detection (Abstract)

J.M. Martinez , Universidad Politecnica de Valencia
P. Lopez , Universidad Politecnica de Valencia
J. Duato , Universidad Politecnica de Valencia
pp. 315
Workshop Overviews

Author Index (PDF)

pp. 323
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