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2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA) (1999)
Orlando, Florida
Jan. 9, 1999 to Jan. 12, 1999
ISBN: 0-7695-0004-8
pp: 300
ABSTRACT
This paper presents the architecture of a router designed to efficiently support traffic generated by multimedia applications. The router is targeted for use in clusters and LANs rather than in WANs, the latter being served by communication substrates such as ATM. The distinguishing features of the proposed router architecture are the use of small fixed-size buffers, a large number of virtual channels, link-level virtual channel flow control, support for dynamic modification of connection bandwidth and priorities, and coordinated scheduling of connections across all output channels. The paper begins with a discussion of the design choices and architectural trade-offs made in the current MultiMedia Router (MMR) project. The performance evaluation section presents some preliminary results of the coordinated scheduling of constant bit rate (CBR) traffic streams.
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CITATION
M. Blanca Caminero, Damon Love, Francisco J. Quiles, Sudhakar Yalamanchili, Jose Duato, "MMR: A High-Performance Multimedia Router - Architecture and Design Trade-Offs", 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA), vol. 00, no. , pp. 300, 1999, doi:10.1109/HPCA.1999.744383
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