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Proceedings Fifth International Symposium on High-Performance Computer Architecture (1999)
Orlando, Florida
Jan. 9, 1999 to Jan. 12, 1999
ISBN: 0-7695-0004-8
pp: 106
Value prediction at the instruction level has been introduced to allow more aggressive speculation and reuse than previous techniques. We investigate the input and output values of basic blocks and find that these values can be quite regular and predictable, suggesting that using compiler support to extend value prediction and reuse to a coarser granularity may have substantial performance benefits. For the SPEC benchmark programs evaluated, 90% of the basic blocks have fewer than 4 register inputs, 5 live register outputs, 4 memory inputs and 2 memory outputs. About 16% to 41% of all the basic blocks are simply repeating earlier calculations when the programs are compiled with the {\it -O2} optimization level in the GCC compiler. We evaluate the potential benefit of basic block reuse using a novel mechanism called a {\it block history buffer}. This mechanism records input and live output values of basic blocks to provide value prediction and reuse at the basic block level. Simulation results show that using a reasonably-sized {\it block history buffer} to provide basic block reuse in a 4-way issue superscalar processor can improve execution time for the tested SPEC programs by 1% to 14% with an overall average of 9%.

D. Lilja and J. Huang, "Exploiting Basic Block Value Locality with Block Reuse," Proceedings Fifth International Symposium on High-Performance Computer Architecture(HPCA), Orlando, Florida, 1999, pp. 106.
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