Proceedings Fifth International Symposium on High-Performance Computer Architecture (1999)
Jan. 9, 1999 to Jan. 12, 1999
This paper proposes and evaluates new synchronization schemes for a simultaneous multithreaded processor. We present a scalable mechanism that permits threads to cheaply synchronize within the processor, with blocked threads consuming no processor resources. We also introduce the concept of lock release prediction, which gains an additional improvement of 40%. Overall, we show that these improvements in synchronization cost enable parallelization of code that could not be effectively parallelized using traditional techniques.
J. L. Lo, D. M. Tullsen, S. J. Eggers and H. M. Levy, "Supporting Fine-Grained Synchronization on a Simultaneous Multithreading Processor," Proceedings Fifth International Symposium on High-Performance Computer Architecture(HPCA), Orlando, Florida, 1999, pp. 54.