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2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA) (1999)
Orlando, Florida
Jan. 9, 1999 to Jan. 12, 1999
ISBN: 0-7695-0004-8
pp: 44
ABSTRACT
Processors that can simultaneously execute multiple paths of execution will only exacerbate the fetch bandwidth problem already plaguing conventional processors. On a multiple-path processor, which speculatively executes less likely paths of hard-to-predict branches, the work done along a speculative path is normally discarded if that path is found to be incorrect. Instead, it can be beneficial to keep these instruction traces stored in the processor for possible future use.This paper introduces instruction recycling, where previously decoded instructions from recently executed paths are injected back into the rename stage. This increases the supply of instructions to the execution pipeline and decreases fetch latency. In addition, if the operands have not changed for a recycled instruction, the instruction can bypass the issue and execution stages, benefiting from instruction reuse. Instruction recycling and reuse are examined for a simultaneous multithreading architecture with multiple path execution. It is shown to increase performance by 7% for single-program workloads and by 12% on multiple-program workloads.
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CITATION
Brad Calder, Steven Wallace, Dean M. Tullsen, "Instruction Recycling on a Multiple-Path Processor", 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA), vol. 00, no. , pp. 44, 1999, doi:10.1109/HPCA.1999.744323
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