The Community for Technology Leaders
2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA) (1999)
Orlando, Florida
Jan. 9, 1999 to Jan. 12, 1999
ISBN: 0-7695-0004-8
pp: 23
Vijay S. Pai , Rice University
Sarita Adve , Rice University
Murthy Durbhakula , Rice University
ABSTRACT
Previous simulators for shared-memory architectures have imposed a large tradeoff between simulation accuracy and speed. Most such simulators model simple processors that do not exploit common instruction-level parallelism (ILP) features, consequently exhibiting large errors when used to model current systems. A few newer simulators model current ILP processors in detail, but we find them to be about ten times slower. We propose a new simulation technique, based on a novel adaptation of direct execution, that alleviates this accuracy vs. speed tradeoff.We compare the speed and accuracy of our new simulator, DirectRSIM, with three other simulators -- RSIM (a detailed simulator for multiprocessors with ILP processors) and two representative simple-processor based simulators. Compared to RSIM, on average, DirectRSIM is 3.6 times faster and exhibits a relative error of only 1.3% in total execution time. Compared to the simple-processor based simulators, DirectRSIM is far superior in accuracy, and yet is only 2.7 times slower.
INDEX TERMS
CITATION
Vijay S. Pai, Sarita Adve, Murthy Durbhakula, "Improving the Accuracy vs. Speed Tradeoff for Simulating Shared-Memory Multiprocessors with ILP Processors", 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA), vol. 00, no. , pp. 23, 1999, doi:10.1109/HPCA.1999.744317
86 ms
(Ver 3.3 (11022016))