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2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA) (1997)
San Antonio, TX
Feb. 1, 1997 to Feb. 5, 1997
ISBN: 0-8186-7764-3
TABLE OF CONTENTS

Referees (PDF)

pp. xi
Session I-A: Novel Memory Architecture

Speeding up the Memory Hierarchy in Flat COMA Multiprocessors (Abstract)

Liuxi Yang , Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign, IL
Josep Torrellas , Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign, IL
pp. 4

Reducing the Replacement Overhead in Bus-Based COMA Multiprocessors (Abstract)

Fredrik Dahlgren , Chalmers University of Technology
Anders Landin , Swedish Institute of Computer Science
pp. 14

Datapath design for a VLIW Video Signal Processor (Abstract)

E.S.T Fernandes , Dept. of Electr. Eng., Princeton Univ., NJ, USA
S. Dutta , Dept. of Electr. Eng., Princeton Univ., NJ, USA
A. Wolfe , Dept. of Electr. Eng., Princeton Univ., NJ, USA
J. Fritts , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 24
Session I-B: Routing and Networks

Distributed Path Reservation Algorithms for Multiplexed All-Optical Interconnection Networks (Abstract)

R. Gupta , Dept. of Comput. Sci., Pittsburgh Univ., PA, USA
X. Yuan , Dept. of Comput. Sci., Pittsburgh Univ., PA, USA
R. Melhem , Dept. of Comput. Sci., Pittsburgh Univ., PA, USA
pp. 38

Multicast on Irregular Switch-based Networks with Wormhole Routing (Abstract)

Ram Kesavan , The Ohio State University, Columbus, OH
Kiran Bondalapati , The Ohio State University, Columbus, OH
Dhabaleswar K. Panda , The Ohio State University, Columbus, OH
pp. 48

A Performance Comparison of Hierarchical Ring- and Mesh- Connected Multiprocessor Networks (Abstract)

Govindan Ravindran , Department of Electrical and Computer Engineering University of Toronto
Michael Stumm , Department of Electrical and Computer Engineering University of Toronto
pp. 58
Session II-A: ILP and Branch Handling

Architectural Support for Compiler-Synthesized Dynamic Branch Prediction Strategies: Rationale and Initial Results (Abstract)

John C. Gyllenhaal , University of Illinois, Urbana-Champaign, IL
David I. August , University of Illinois, Urbana-Champaign, IL
Daniel A. Connors , University of Illinois, Urbana-Champaign, IL
Wen-mei W. Hwu , University of Illinois, Urbana-Champaign, IL
pp. 84

Multiple Branch and Block Prediction (Abstract)

Steven Wallace , University of California, Irvine
Nader Bagherzadeh , University of California, Irvine
pp. 94
Session II-B: Efficient Communications

Evaluating MPI Collective Communication on the SP2, T3D, and Pargon Multicomputers (Abstract)

Kai Hwang , The University of Hong Kong, Pokfulam, Hong Kong
Cho-Li Wang , The University of Hong Kong, Pokfulam, Hong Kong
Choming Wang , The University of Hong Kong, Pokfulam, Hong Kong
pp. 106

Message Proxies for Efficient, Protected Communication on SMP Clusters (Abstract)

P. Pattnaik , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
M. Snir , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
B-H. Lim , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
P. Heidelberger , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 116

Scheduling Communication on an SMP Node Parallel Machine (Abstract)

David A. Wood , University of Wisconsin - Madison
Babak Falsafi , University of Wisconsin - Madison
pp. 128
Panel Session: Shared-Memory Multiprocessors
Session III-A: Memory Systems

Design Issues and Tradeoffs for Write Buffers (Abstract)

Douglas W. Clark , Princeton University
Kevin Skadron , Princeton University
pp. 144

Software-Managed Address Translation (Abstract)

T. Mudge , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
B. Jacob , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 156

Global Address Space, Non-Uniform Bandwidth: A Memory System Performance Characterization of Parallel Systems (Abstract)

T. Cross , Sch. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA
T. Stricker , Sch. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 168
Session III-B: Communication-Efficient Cache Architectures

On the Use and Performance of Explicit Communication Primitives in Cache-coherent Multiprocessor Systems (Abstract)

Jean-Loup Baer , University of Washington, Seattle, WA
Xiaohan Qin , University of Washington, Seattle, WA
pp. 182

Reducing the Communication Overhead of Dynamic Applications on Shared Memory Multiprocessors (Abstract)

A. Sivasubramaniam , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
pp. 194
Session IV-A: High-Performance Processors

Control Flow Speculation in Multiscalar Processors (Abstract)

Quinn Jacobson , University of Wisconsin - Madison
Steve Bennett , University of Wisconsin - Madison
James E. Smith , University of Wisconsin - Madison
Nikhil Sharma , University of Wisconsin - Madison
pp. 218

Advances of the Counterflow Pipeline Microarchitecture (Abstract)

Shih-Lien Lu , Oregon State University
Kennneth J. Janik , Oregon State University
Michael F. Miller , Oregon State University
pp. 230

Multithreaded Vector Architectures (Abstract)

Mateo Valero , Universitat Politecnica Catalunya, Barcelona
Roger Espasa , Universitat Politecnica Catalunya, Barcelona
pp. 237
Session IV-B: Shared-Memory Multiprocessors

Software DSM Protocols that Adapt between Single Writer and Multiple Writer (Abstract)

Sandhya Dwarkadas , University of Rochester
Cristiana Amza , Rice University
Willy Zwaenepoel , Rice University
Alan L. Cox , Rice University
pp. 261

Reducing Remote Conflict Misses: NUMA with Remote Cache versus COMA (Abstract)

Zheng Zhang , University of Illinois at Urbana-Champaign, IL
Josep Torrellas , University of Illinois at Urbana-Champaign, IL
pp. 272
Panel Session: Computer Architecture Research for a New Century
Session V-A: Performance Evaluation and Characterization

Performance Characterization of the Pentium? Pro Processor (Abstract)

Jason Ding , Intel Corporation
Dileep Bhandarkar , Intel Corporation
pp. 288

A Framework for Statistical Modeling of Superscalar Processor Performance (Abstract)

John Paul Shen , Carnegie Mellon University
Derek B. Noonburg , Carnegie Mellon University
pp. 298

Towards a Communication Characterization Methodology for Parallel Applications (Abstract)

Aniruddha S. Vaidya , The Pennsylvania State University
Anand Sivasubramaniam , The Pennsylvania State University
Viji Srinivasan , The Pennsylvania State University
Sucheta Chodnekar , The Pennsylvania State University
Chita R. Das , The Pennsylvania State University
pp. 310
Session V-B: Network Interface

User-Level DMA without Operating System Kernel Modification (Abstract)

Manolis G.H. Katevenis , Institute of Computer Science (ICS) Foundation for Research & Technology -- Hellas (FORTH)
Evangelos P. Markatos , Institute of Computer Science (ICS) Foundation for Research & Technology -- Hellas (FORTH)
pp. 322

ATM and Fast Ethernet Network Interfaces for User-level Communication (Abstract)

Thorsten von Eicken , Cornell University
Matt Welsh , Cornell University
Anindya Basu , Cornell University
pp. 332

Architectural Support for Reducing Communication Overhead in Multiprocessor Interconnection Networks (Abstract)

Jose Duato , Universidad Politecnica de Valencia
Sudhakar Yalamanchili , Georgia Institute of Technology
Binh Vien Dao , Georgia Institute of Technology
pp. 343

Author Index (PDF)

pp. 353
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