2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA) (1997)
San Antonio, TX
Feb. 1, 1997 to Feb. 5, 1997
T. Mudge , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
B. Jacob , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
In this paper we explore software-managed address translation. The purpose of the study is to specify the memory management design for a high clock-rate PowerPC implementation in which a simple design is a prerequisite for a fast clock and a short design cycle. We show that software-managed address translation is just as efficient as hardware-managed address translation and it is much more flexible. Operating systems such as OSF/1 and Mach charge between 0.10 and 0.28 cycles per instruction (CPI) for address translation using dedicated memory-management hardware. Software-managed translation requires 0.05 CPI. Mechanisms to support such features as shared memory, superpages, sub-page protection, and sparse address spaces can be defined completely in software, allowing much more flexibility than in hardware-defined mechanisms.
storage management, software-managed address translation, memory management design, high clock-rate PowerPC implementation, OSF/1, Mach, shared memory, superpages, sub-page protection, sparse address spaces
T. Mudge, B. Jacob, "Software-Managed Address Translation", 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA), vol. 00, no. , pp. 156, 1997, doi:10.1109/HPCA.1997.569652