The Community for Technology Leaders
2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA) (1997)
San Antonio, TX
Feb. 1, 1997 to Feb. 5, 1997
ISBN: 0-8186-7764-3
pp: 94
Steven Wallace , University of California, Irvine
Nader Bagherzadeh , University of California, Irvine
ABSTRACT
Accurate branch prediction and instruction fetch prediction of a microprocessor are critical to achieve high performance. For a processor which fetches and executes multiple instructions per cycle, an accurate and high bandwidth instruction fetching mechanism becomes increasingly important to performance. Unfortunately, the relatively small basic block size exhibited in many general-purpose applications severely limits instruction fetching. In order to achieve a high fetching rate for wide-issue superscalars, a scalable method to predict multiple branches per block of sequential instructions is presented. Its accuracy is equivalent to a scalar two-level adaptive prediction. Also, to overcome the limitation imposed by control transfers, a scalable method to predict multiple blocks is presented. As a result, a two block, multiple branch prediction mechanism for a block width of 8 instructions achieves an effective fetching rate of 8 instructions per cycle on the SPEC95 benchmark suite.
INDEX TERMS
CITATION
Steven Wallace, Nader Bagherzadeh, "Multiple Branch and Block Prediction", 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA), vol. 00, no. , pp. 94, 1997, doi:10.1109/HPCA.1997.569645
80 ms
(Ver 3.3 (11022016))