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Proceedings. Second International Symposium on High-Performance Computer Architecture (1996)
San Jose, CA
Feb. 3, 1996 to Feb. 7, 1996
ISBN: 0-8186-7237-4
TABLE OF CONTENTS

Proceedings. Second International Symposium on High-Performance Computer Architecture (PDF)

pp. i

Message from the General Chair (PDF)

pp. viii

Message from the Program Chair (PDF)

pp. ix

HPCA 1996 Chairs and Committees (PDF)

pp. x

Referees (PDF)

pp. xi
Session I-A: Network of Workstations

Performance Evaluation of a Cluster-Based Multiprocessor Built from ATM Switches and Bus-Based Multiprocessor Servers (Abstract)

Magnus Karlsson , Chalmers University of Technology
Per Stenström , Chalmers University of Technology
pp. 4

Improving Release-Consistent Shared Virtual Memory using Automatic Update (Abstract)

Liviu Iftode , Department of Computer Science Princeton University
Cezary Dubnicki , Department of Computer Science Princeton University
Edward W. Felten , Department of Computer Science Princeton University
Kai Li , Department of Computer Science Princeton University
pp. 14

A Comparison of Entry Consistency and Lazy Release Consistency Implementations (Abstract)

Sarita V. Adve , Rice University
Alan L. Cox , Rice University
Sandhya Dwarkadas , Rice University
Ramakrishnan Rajamony , Rice University
Willy Zwaenepoel , Rice University
pp. 26
Session I-B: Instruction Scheduling

Register File Design Considerations in Dynamically Scheduled Processors (Abstract)

Keith I. Farkas , University of Toronto
Paul Chow , University of Toronto
Norman P. Jouppi , Digital Equipment Corporation
pp. 40

Co-Scheduling Hardware and Software Pipelines (Abstract)

R. Govindarajan
Erik R. Altman
Guang R. Gao
pp. 52

Representative Traces for Processor Models with Infinite Cache (Abstract)

Vijay S. Iyengar , IBM Research Division Thomas J. Watson Research Center
Louise H. Trevillyan , IBM Research Division Thomas J. Watson Research Center
Pradip Bose , IBM Research Division Thomas J. Watson Research Center
pp. 62
Session II-A: Shared-Memory Multiprocessors

The impact of shared-cache clustering in small-scale shared-memory multiprocessors (Abstract)

B.A. Nayfeh , Comput. Syst. Lab., Stanford Univ., CA, USA
K. Olukotun , Comput. Syst. Lab., Stanford Univ., CA, USA
J.P. Singh , Comput. Syst. Lab., Stanford Univ., CA, USA
pp. 74

Improving the Data Cache Performance of Multiprocessor Operating Systems (Abstract)

Chun Xia , Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign
Josep Torrellas , Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign
pp. 85

Bus-based COMA-reducing traffic in shared-bus multiprocessors (Abstract)

A. Landin , Swedish Inst. of Comput. Sci., Kista, Sweden
F. Dahlgren , Swedish Inst. of Comput. Sci., Kista, Sweden
pp. 95
Session II-B: Interconnection Networks

RMB -- A Reconfigurable Multiple Bus Network (Abstract)

H. ElGindy , The University of Newcastle
A. K. Somani , University of Washington
H. Schroder , Loughborough University of Technology Loughborough
H. Schmeck , Universitat Karlsruhe
A. Spray , The University of Newcastle
pp. 108

On the Multiplexing Degree Required to Embed Permutations in a Class of Networks with Direct Interconnects (Abstract)

Chunming Qiao , Department of Electrical and Computer Engineering State University of New York at Buffalo
Yousong Mei , Department of Electrical and Computer Engineering State University of New York at Buffalo
pp. 118

The Shuffle-Ring: Overcoming the Increasing Degree of Hypercube (Abstract)

Guihai Chen , University of Hong Kong
Francis C. M. Lau , University of Hong Kong
pp. 130
Session III-A: Network Interfaces

Telegraphos: High-Performance Networking for Parallel Processing on Workstation Clusters (Abstract)

Evangelos P. Markatos , Institute of Computer Science (ICS) Foundation for Research & Technology -- Hellas (FORTH)
Manolis G.H. Katevenis , Institute of Computer Science (ICS) Foundation for Research & Technology -- Hellas (FORTH)
pp. 144

Protected, user-level DMA for the SHRIMP network interface (Abstract)

M.A. Blumrich , Dept. of Comput. Sci., Princeton Univ., NJ, USA
C. Dubnicki , Dept. of Comput. Sci., Princeton Univ., NJ, USA
E.W. Felten , Dept. of Comput. Sci., Princeton Univ., NJ, USA
Kai Li , Dept. of Comput. Sci., Princeton Univ., NJ, USA
pp. 154

Using memory-mapped network interfaces to improve the performance of distributed shared memory (Abstract)

L.I. Kontothanassis , Dept. of Comput. Sci., Rochester Univ., NY, USA
M.L. Scott , Dept. of Comput. Sci., Rochester Univ., NY, USA
pp. 166
Session III-B: Network Routing

Fault-Tolerant Multicast Routing in the Mesh with No Virtual Channels (Abstract)

Ran Libeskind-Hadas
Kevin Watkins
Thomas Hehre
pp. 180

A Topology-Independent Generic Methodology for Deadlock-Free Wormhole Routing (Abstract)

Hyunmin Park , North Carolina State University
Dharma P. Agrawal , North Carolina State University
pp. 191

Fault-Tolerance with Multimodule Routers (Abstract)

Suresh Chalasani , Univ. of Wisconsin-Madison
Rajendra Boppana , Univ. of Texas at San Antonio
pp. 201
Session IV-A: Multiprocessor Systems

Multitasking and Multithreading on a Multiprocessor with Virtual Shared Memory (Abstract)

Henk L. Muller , Department of Computer Science, University of Bristol, UK. Working at: Partnership in Advanced Computing Technologies Science Research Foundation, 10 Priory Road, Bristol. BS8 1TU, UK.
Paul W.A. Stallard , Department of Computer Science, University of Bristol, UK. Working at: Partnership in Advanced Computing Technologies Science Research Foundation, 10 Priory Road, Bristol. BS8 1TU, UK.
David H.D. Warren , Department of Computer Science, University of Bristol, UK. Working at: Partnership in Advanced Computing Technologies Science Research Foundation, 10 Priory Road, Bristol. BS8 1TU, UK.
pp. 212

A Cache Coherency Protocol for Optically Connected Parallel Computer Systems (Abstract)

John Reisner , Headquarters, Standard Systems Group Automated Communications Systems Directorate
Tom S. Wailes , Air Force Institute of Technology
pp. 222

Parallel Intersecting Compressed Bit Vectors in a High Speed Query Server for Processing Postal (Abstract)

Wen-jann Yang , Department of Electrical and Computer Engineering The State University of New York at Buffalo
Ramalingam Sridhar , Department of Electrical and Computer Engineering The State University of New York at Buffalo
Victor Demjanenko , Department of Electrical and Computer Engineering The State University of New York at Buffalo
pp. 232
Session IV-B: Caches

Predictive sequential associative cache (Abstract)

B. Calder , Dept. of Comput. Sci., Colorado Univ., Boulder, CO, USA
D. Grunwald , Dept. of Comput. Sci., Colorado Univ., Boulder, CO, USA
J. Emer , Dept. of Comput. Sci., Colorado Univ., Boulder, CO, USA
pp. 244

Distributed Prefetch-buffer/Cache Design for High Performance Memory Systems (Abstract)

Thomas Alexander , Departments of Computer Science and Electrical Engineering Duke University
Gershon Kedem , Departments of Computer Science and Electrical Engineering Duke University
pp. 254
Session V-A: High-Performance Processors

Performance Characterization of the Alpha 21164 Microprocessor Using TP and SPEC Workloads (Abstract)

Zarka Cvetanovic , Digital Equipment Corporation
Dileep Bhandarkar , Intel Corporation
pp. 270

Decoupled vector architectures (Abstract)

R. Espasa , Dept. d'Arquitectura de Computadors, Univ. Politecnica de Catalunya, Barcelona, Spain
M. Valero , Dept. d'Arquitectura de Computadors, Univ. Politecnica de Catalunya, Barcelona, Spain
pp. 281

Performance Study of a Multithreaded Superscalar Microprocessor (Abstract)

Manu Gulati , NexGen Inc.
Nader Bagherzadeh , Electrical and Computer Engineering University of California, Irvine, CA 92714
pp. 291
Session V-B: Cache Protocols

Two Adaptive Hybrid Cache Coherency Protocols (Abstract)

Craig Anderson , Apple Computer
Anna R. Karlin , Department of Computer Science and Engineering University of Washington
pp. 303

A Shared-bus Control Mechanism and a Cache Coherence Protocol for a High-performance On-chip Multiprocessor (Abstract)

Masafumi Takahashi , Research and Development Center, Toshiba Corporation
Hiroyuki Takano , Research and Development Center, Toshiba Corporation
Emi Kaneko , Research and Development Center, Toshiba Corporation
Seigo Suzuki , Research and Development Center, Toshiba Corporation
pp. 314

Distance-Adaptive Update Protocols for Scalable Shared-Memory Multiprocessors (Abstract)

Alain Raynaud , Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign
Zheng Zhang , Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign
Josep Torrellas , Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign
pp. 323

Author Index (PDF)

pp. 335
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