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2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA) (1996)
San Jose, CA
Feb. 3, 1996 to Feb. 7, 1996
ISBN: 0-8186-7237-4
pp: 95
A. Landin , Swedish Inst. of Comput. Sci., Kista, Sweden
F. Dahlgren , Swedish Inst. of Comput. Sci., Kista, Sweden
ABSTRACT
A problem with bus-based shared-memory multiprocessors is that the shared bus rapidly becomes a bottleneck in the machine, effectively limiting the machine size to somewhere between ten and twenty processors. We propose a new architecture, the bus-based COMA (BB-COMA) that addresses this problem. Compared to the standard UMA architecture, the BE-COMA has lower requirements on bus bandwidth. We have used program-driven simulation to study the two architectures running applications from the SPLASH suite. We observed a traffic reduction of up to 70% for BB-COMA, with an average of 46%, for the programs studied. The results indicate that the BB-COMA is an interesting candidate architecture for future implementations of shared-bus multiprocessors.
INDEX TERMS
shared memory systems; memory architecture; cache storage; bus-based COMA; shared-bus multiprocessors; shared-memory multiprocessors; standard UMA architecture; program-driven simulation; SPLASH; cache only memory architecture
CITATION
A. Landin, F. Dahlgren, "Bus-based COMA-reducing traffic in shared-bus multiprocessors", 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA), vol. 00, no. , pp. 95, 1996, doi:10.1109/HPCA.1996.501177
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