2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA) (1996)
San Jose, CA
Feb. 3, 1996 to Feb. 7, 1996
Josep Torrellas , Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign
Chun Xia , Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign
Bus-based shared-memory multiprocessors with coherent caches have recently become very popular. To achieve high performance, these systems rely on increasingly sophisticated cache hierarchies. However, while these machines often run loads with substantial operating system activity, performance measurements have consistently indicated that the operating system uses the data cache hierarchy poorly. In this paper, we address the issue of how to eliminate most of the data cache misses in a multiprocessor operating system while still using off-the-shelf processors. We use a performance monitor to examine traces of a 4-processor machine running four system-intensive loads under UNIX. Based on our observations, we propose hardware and software support that targets block operations, coherence activity, and cache conflicts. For block operations, simple cache bypassing or prefetching schemes are undesirable. Instead, it is best to use a DMA-like scheme that pipelines the data transfer in the bus without involving the processor. Coherence misses are handled with data privatization and relocation, and the use of updates for a small core of shared variables. Finally, the remaining miss hot spots are handled with data prefetching. Overall, our simulations show that all these optimizations combined eliminate or hide 75% of the operating system data misses in 32-Kbyte primary caches. Furthermore, they speed up the operating system by 19%.
data cache performance, operating system effect on caches, bus-based multiprocessor, address trace evaluation, block operations, latency hiding
Josep Torrellas, Chun Xia, "Improving the Data Cache Performance of Multiprocessor Operating Systems", 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA), vol. 00, no. , pp. 85, 1996, doi:10.1109/HPCA.1996.501176