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2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA) (1996)
San Jose, CA
Feb. 3, 1996 to Feb. 7, 1996
ISBN: 0-8186-7237-4
pp: 62
Louise H. Trevillyan , IBM Research Division Thomas J. Watson Research Center
Vijay S. Iyengar , IBM Research Division Thomas J. Watson Research Center
Pradip Bose , IBM Research Division Thomas J. Watson Research Center
ABSTRACT
Performance evaluation of processor designs using dynamic instruction traces is a critical part of the iterative design process. The widening gap between the billions of instructions in such traces for benchmark programs and the throughput of timers performing the analysis in the tens of thousands of instructions per second has led to the use of reduced traces during design. This opens up the issue of whether these traces are truly representative of the actual workload in these benchmark programs. The first key result in this paper is the introduction of a new metric, called the R-metric, to evaluate the representativeness of these reduced traces when applied to a wide class of processor designs. The second key result, is the development of a novel graph-based heuristic to generate reduced traces based on the notions incorporated in the metric. These ideas have been implemented in a prototype system (SMART) for generating representative and reduced traces. Extensive experimental results are presented on various benchmarks to demonstrate the quality of the synthetic traces and the uses of the R-metric.
INDEX TERMS
dynamic traces, timer, performance evaluation, processor design
CITATION
Louise H. Trevillyan, Vijay S. Iyengar, Pradip Bose, "Representative Traces for Processor Models with Infinite Cache", 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA), vol. 00, no. , pp. 62, 1996, doi:10.1109/HPCA.1996.501174
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