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2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA) (1996)
San Jose, CA
Feb. 3, 1996 to Feb. 7, 1996
ISBN: 0-8186-7237-4
pp: 40
Paul Chow , University of Toronto
Keith I. Farkas , University of Toronto
Norman P. Jouppi , Digital Equipment Corporation
We have investigated the register file requirements of dynamically scheduled processors using register renaming and dispatch queues running the SPEC92 benchmarks. We looked at processors capable of issuing either four or eight instructions per cycle and found that in most cases implementing precise exceptions requires a relatively small number of additional registers compared to imprecise exceptions. Systems with aggressive non-blocking load support were able to achieve performance similar to processors with perfect memory systems at the cost of some additional registers. Given our machine assumptions, we found that the performance of a four-issue machine with a 32-entry dispatch queue tends to saturate around 80 registers. For an eight-issue machine with a 64-entry dispatch queue performance does not saturate until about 128 registers. Assuming the machine cycle time is proportional to the register file cycle time, the 8-issue machine yields only 20% higher performance than the 4-issue machine due in part to the cycle time impact of additional hardware.
dynamic scheduling, register files, register renaming
Paul Chow, Keith I. Farkas, Norman P. Jouppi, "Register File Design Considerations in Dynamically Scheduled Processors", 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA), vol. 00, no. , pp. 40, 1996, doi:10.1109/HPCA.1996.501172
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