The Community for Technology Leaders
2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA) (1995)
Raleigh, North Carolina
Jan. 22, 1995 to Jan. 25, 1995
ISBN: 0-8186-6445-2
TABLE OF CONTENTS

Referees (PDF)

pp. xi
Session I-A Register Management
Session I-B: Interconnection Networks

Reducing communication latency with path multiplexing: in optically interconnected multiprocessor systems (Abstract)

Chunming Qiao , Dept. of Electr. & Comput. Eng., State Univ. of New York, Buffalo, NY, USA
R. Melhem , Dept. of Electr. & Comput. Eng., State Univ. of New York, Buffalo, NY, USA
pp. 34

Abstracting network characteristics and locality properties of parallel systems (Abstract)

H. Venkateswaran , Coll. of Comput., Georgia Inst. of Technol., Atlanta, GA, USA
U. Ramachandran , Coll. of Comput., Georgia Inst. of Technol., Atlanta, GA, USA
A. Sivasubramaniam , Coll. of Comput., Georgia Inst. of Technol., Atlanta, GA, USA
M. Singla , Coll. of Comput., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 54
Session II-A: Latency Reduction Techniques

Effectiveness of hardware-based stride and sequential prefetching in shared-memory multiprocessors (Abstract)

P. Stenstrom , Dept. of Comput. Eng., Lund Univ., Sweden
F. Dahlgren , Dept. of Comput. Eng., Lund Univ., Sweden
pp. 68

Creating a wider bus using caching techniques (Abstract)

L. Rudolph , Inst. of Comput. Sci., Hebrew Univ., Jerusalem, Israel
D. Citron , Inst. of Comput. Sci., Hebrew Univ., Jerusalem, Israel
pp. 90
Session II-B: Routing in Mesh

Origin-based fault-tolerant routing in the mesh (Abstract)

E. Brandt , Dept. of Comput. Sci., Harvey Mudd Coll., Claremont, CA, USA
R. Libeskind-Hadas , Dept. of Comput. Sci., Harvey Mudd Coll., Claremont, CA, USA
pp. 102

Efficient and balanced adaptive routing in two-dimensional meshes (Abstract)

V. Varavithya , Dept. of Electr. Eng. & Comput. Eng., Iowa State Univ., Ames, IA, USA
P. Mohapatra , Dept. of Electr. Eng. & Comput. Eng., Iowa State Univ., Ames, IA, USA
J.H. Upadhyay , Dept. of Electr. Eng. & Comput. Eng., Iowa State Univ., Ames, IA, USA
pp. 112

Fault-tolerant adaptive routing for two-dimensional meshes (Abstract)

C.M. Cunningham , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
D.R. Avresky , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
pp. 122
Session III-A: Cache Memory

DASC cache (Abstract)

A. Seznec , IRISA, Rennes, France
pp. 134

Software assistance for data caches (Abstract)

O. Temam , PRiSM Lab., Versailles Univ., France
N. Drach , PRiSM Lab., Versailles Univ., France
pp. 154
Session III B: Modeling and Performance Evaluation

Modeling virtual channel flow control in hypercubes (Abstract)

Y.M. Boura , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
C.R. Das , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
pp. 166

Simulation study of cached RAID5 designs (Abstract)

J. Menon , IBM Almaden Res. Center, San Jose, CA, USA
R. Treiber , IBM Almaden Res. Center, San Jose, CA, USA
pp. 186
Session IV-A: Synchronization and Scheduling

Fast barrier synchronization in wormhole k-ary n-cube networks with multidestination worms (Abstract)

D.K. Panda , Dept. of Comput. & Inf. Sci., Ohio State Univ., Columbus, OH, USA
pp. 200

Thread prioritization: a thread scheduling mechanism for multiple-context parallel processors (Abstract)

W.J Dally , Artificial Intelligence Lab., MIT, Cambridge, MA, USA
S. Fiske , Artificial Intelligence Lab., MIT, Cambridge, MA, USA
pp. 222
Session IV-B: Memory Management

Improving performance by cache driven memory management (Abstract)

K. Westerholz , Corp. Res. & Dev., Siemens AG, Munich, Germany
S. Honal , Corp. Res. & Dev., Siemens AG, Munich, Germany
C. Hafer , Corp. Res. & Dev., Siemens AG, Munich, Germany
J. Plankl , Corp. Res. & Dev., Siemens AG, Munich, Germany
pp. 234

U-cache: a cost-effective solution to synonym problem (Abstract)

Byoungchu Ahn , Dept. of Comput. Eng., Seoul Nat. Univ., South Korea
Sang Lyul Min , Dept. of Comput. Eng., Seoul Nat. Univ., South Korea
Sanghoon Jeon , Dept. of Comput. Eng., Seoul Nat. Univ., South Korea
Deog-Kyoon Jeong , Dept. of Comput. Eng., Seoul Nat. Univ., South Korea
Chong Sang Kim , Dept. of Comput. Eng., Seoul Nat. Univ., South Korea
Jesung Kim , Dept. of Comput. Eng., Seoul Nat. Univ., South Korea
pp. 243

Access ordering and memory-conscious cache utilization (Abstract)

W.A. Wulf , Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA
S.A. Mckee , Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA
pp. 253
Session V-A: Cache Coherence

Two techniques for improving performance on bus-based multiprocessors (Abstract)

J.-L. Baer , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
C. Anderson , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
pp. 264

An argument for simple COMA (Abstract)

A. Landin , Inst. of Comput. Sci., Kista, Sweden
J. Carter , Inst. of Comput. Sci., Kista, Sweden
T. Wilkinson , Inst. of Comput. Sci., Kista, Sweden
A. Saulsbury , Inst. of Comput. Sci., Kista, Sweden
pp. 276

Software cache coherence for large scale multiprocessors (Abstract)

M.L. Scott , Dept. of Comput. Sci., Rochester Univ., NY, USA
L.I. Kontothanassis , Dept. of Comput. Sci., Rochester Univ., NY, USA
pp. 286
Session V-B: Multithreaded Architecture

Design and performance evaluation of a multithreaded architecture (Abstract)

R. Govindarajan , Dept. of Comput. Sci., Memorial Univ. of Newfoundland, St. John's, Nfld., Canada
P. LeNir , Dept. of Comput. Sci., Memorial Univ. of Newfoundland, St. John's, Nfld., Canada
S.S. Nemawarkar , Dept. of Comput. Sci., Memorial Univ. of Newfoundland, St. John's, Nfld., Canada
pp. 298

Fine-grain multi-thread processor architecture for massively parallel processing (Abstract)

R.-I. Taniguchi , Dept. of Inf. Syst., Kyushu Univ., Fukuoka, Japan
S. Kusakabe , Dept. of Inf. Syst., Kyushu Univ., Fukuoka, Japan
M. Amamiya , Dept. of Inf. Syst., Kyushu Univ., Fukuoka, Japan
T. Kawano , Dept. of Inf. Syst., Kyushu Univ., Fukuoka, Japan
pp. 308

The effects of STEF in finely parallel multithreaded processors (Abstract)

Wanming Chu , Comput. Archit. Lab., Aizu Univ., Japan
Yamin Li , Comput. Archit. Lab., Aizu Univ., Japan
pp. 318
Session VI-A: Special Purpose Architectures

Massively parallel array processor for logic, fault, and design error simulation (Abstract)

Y. Hur , ECE Dept., Texas Univ., Austin, TX, USA
E. Scott Fehr , ECE Dept., Texas Univ., Austin, TX, USA
Sungho Kang , ECE Dept., Texas Univ., Austin, TX, USA
S.A. Szygenda , ECE Dept., Texas Univ., Austin, TX, USA
G.E. Ott , ECE Dept., Texas Univ., Austin, TX, USA
pp. 340

Architectural support for inter-stream communication in a MSIMD system (Abstract)

D.E. Schimmel , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
V. Garg , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 348
Session VI-B: Code Optimization

Optimizing instruction cache performance for operating system intensive workloads (Abstract)

J. Torrellas , Center for Supercomput. Res. & Dev., Illinois Univ., Urbana, IL, USA
Chun Xia , Center for Supercomput. Res. & Dev., Illinois Univ., Urbana, IL, USA
R. Daigle , Center for Supercomput. Res. & Dev., Illinois Univ., Urbana, IL, USA
pp. 360

Program balance and its impact on high performance RISC architectures (Abstract)

L.D. Coraor , Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
V. Reddy , Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
L.K. John , Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
P.T. Hulina , Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
pp. 370

Memory access reordering in vector processors (Abstract)

De-Lei Lee , Dept. of Comput. Sci., York Univ., Toronto, Ont., Canada
pp. 380
Invited Session II: Uniprocessor Architectures for High Performance: Organizer: Yale Patt, University of Michigan

Author Index (PDF)

pp. 393
103 ms
(Ver 3.3 (11022016))