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Proceedings of 1995 1st IEEE Symposium on High Performance Computer Architecture (1995)
Raleigh, North Carolina
Jan. 22, 1995 to Jan. 25, 1995
ISBN: 0-8186-6445-2
pp: 286
L.I. Kontothanassis , Dept. of Comput. Sci., Rochester Univ., NY, USA
M.L. Scott , Dept. of Comput. Sci., Rochester Univ., NY, USA
Shared memory is an appealing abstraction for parallel programming. It must be implemented with caches in order to perform well, however and caches require a coherence mechanism to ensure that processors reference current data. Hardware coherence mechanisms for large-scale machines are complex and costly, but existing software mechanisms for message-passing machines have not provided a performance-competitive solution. We claim that an intermediate hardware option-memory-mapped network interfaces that support a global physical address space-can provide most of the performance benefits of hardware cache coherence. We present a software coherence protocol that runs on this class of machines and greatly narrows the performance gap between hardware and software coherence. We compare the performance of the protocol to that of existing software and hardware alternatives and evaluate the tradeoffs among various cache-write policies. We also observe that simple program changes can greatly improve performance. For the programs in our test suite and with the changes in place, software coherence is often faster and never more than 55% slower than hardware coherence.
shared memory systems; cache storage; message passing; concurrency control; large scale multiprocessors; software cache coherence; hardware coherence mechanisms; message-passing machines; memory-mapped network interfaces; global physical address space; software coherence protocol; cache-write policies

M. Scott and L. Kontothanassis, "Software cache coherence for large scale multiprocessors," Proceedings of 1995 1st IEEE Symposium on High Performance Computer Architecture(HPCA), Raleigh, North Carolina, 1995, pp. 286.
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