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Proceedings of 1995 1st IEEE Symposium on High Performance Computer Architecture (1995)
Raleigh, North Carolina
Jan. 22, 1995 to Jan. 25, 1995
ISBN: 0-8186-6445-2
pp: 253
S.A. Mckee , Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA
W.A. Wulf , Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA
ABSTRACT
As processor speeds increase relative to memory speeds, memory bandwidth is rapidly becoming the limiting performance, factor for many applications. Several approaches to bridging this performance gap have been suggested. This paper examines one approach, access ordering, and pushes its limits to determine bounds on memory performance. We present several access-ordering schemes, and compare their performance, developing analytic models and partially validating these with benchmark timings on the Intel i860XR.
INDEX TERMS
cache storage; storage management; performance evaluation; memory-conscious cache utilization; memory bandwidth; access ordering; memory performance; analytic models; Intel i860XR; benchmark timings
CITATION

W. Wulf and S. Mckee, "Access ordering and memory-conscious cache utilization," Proceedings of 1995 1st IEEE Symposium on High Performance Computer Architecture(HPCA), Raleigh, North Carolina, 1995, pp. 253.
doi:10.1109/HPCA.1995.386537
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