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2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA) (1995)
Raleigh, North Carolina
Jan. 22, 1995 to Jan. 25, 1995
ISBN: 0-8186-6445-2
pp: 90
L. Rudolph , Inst. of Comput. Sci., Hebrew Univ., Jerusalem, Israel
D. Citron , Inst. of Comput. Sci., Hebrew Univ., Jerusalem, Israel
ABSTRACT
The effective bandwidth of a bus and external communication ports can be increased by using a variant of data compression techniques that compacts words instead of data streams. The compaction is performed by caching the high order bits into a table and sending the index into the table along with the low order bits. A coherent table at the receiving end expands the word into it original form. Compaction/expansion units can be placed between processor and memory, between processor and local bus, and between devices that access the system bus. Simulations have shown that over 90% of all informative transferred can be sent in a single cycle when using a 32 bit processor connected by a 16 bit wide bus to a 32 bit memory module. This is for all forms of data, address, data, and instructions, and when a cache-based processor is used.
INDEX TERMS
system buses; cache storage; data compression; caching techniques; effective bandwidth; external communication ports; data compression techniques; memory module; cache-based processor; 16 bit; 32 bit
CITATION
L. Rudolph, D. Citron, "Creating a wider bus using caching techniques", 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA), vol. 00, no. , pp. 90, 1995, doi:10.1109/HPCA.1995.386552
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