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2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA) (1995)
Raleigh, North Carolina
Jan. 22, 1995 to Jan. 25, 1995
ISBN: 0-8186-6445-2
pp: 68
P. Stenstrom , Dept. of Comput. Eng., Lund Univ., Sweden
F. Dahlgren , Dept. of Comput. Eng., Lund Univ., Sweden
ABSTRACT
We study the relative efficiency of previously proposed stride and sequential prefetching-two promising hardware-based prefetching schemes to reduce read-miss penalties in shared-memory multiprocessors. Although stride accesses dominate in four out of six of the applications we study, we find that sequential prefetching does better than stride prefetching for three applications. This is because (i) most strides are shorter than the block size (we assume 32 byte blocks), which means that sequential prefetching is as effective for stride accesses, and (ii) sequential prefetching also exploits the locality of read misses for non-stride accesses. However we find that since stride prefetching causes fewer useless prefetches, it consumes less memory-system bandwidth.
INDEX TERMS
shared memory systems; cache storage; communication complexity; storage management; multiprocessor interconnection networks; hardware-based stride prefetching; hardware-based sequential prefetching; shared-memory multiprocessors; read-miss penalties; read misses; memory-system bandwidth
CITATION
P. Stenstrom, F. Dahlgren, "Effectiveness of hardware-based stride and sequential prefetching in shared-memory multiprocessors", 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA), vol. 00, no. , pp. 68, 1995, doi:10.1109/HPCA.1995.386554
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