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2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA) (1995)
Raleigh, North Carolina
Jan. 22, 1995 to Jan. 25, 1995
ISBN: 0-8186-6445-2
pp: 44
F. Cappello , Univ. de Paris-Sud, Orsay, France
C. Germain , Univ. de Paris-Sud, Orsay, France
ABSTRACT
This paper discusses a new principle of interconnection network for massively parallel architectures in the field of numerical computation. The principle is motivated by an analysis of the application features and the need to design new kind of communication networks combining very high bandwidth, very low latency, performance independence to communication pattern or network load and a performance improvement proportional to the hardware performance improvement. Our approach is to associate compiled communications and a circuit switched interconnection network. This paper presents the motivations for this principle, the hardware and software issues and the design of a first prototype. The expected performance are a sustained aggregate bandwidth of more than 500 GBytes/s and an overall latency less than 270 ns, for a large implementation (4K inputs) with the current available technology.
INDEX TERMS
multiprocessor interconnection networks; parallel architectures; communication complexity; high communication performance; compiled communications; circuit switched interconnection network; massively parallel architectures; numerical computation; application features; communication networks; communication pattern; network load
CITATION
F. Cappello, C. Germain, "Toward high communication performance through compiled communications on a circuit switched interconnection network", 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA), vol. 00, no. , pp. 44, 1995, doi:10.1109/HPCA.1995.386556
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