Implementation Register Interlocks in Parallel-Pipeline, Multiple Instruction Queue, Superscalar Processors
2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA) (1995)
Raleigh, North Carolina
Jan. 22, 1995 to Jan. 25, 1995
A dependence for data, control, or resources might cause one instruction to become stalled in a pipeline stage waiting for a preceding instruction to produce a result or release a resource. The pipeline control hardware checks for dependences, and prevents the instruction from going to the next pipeline stage if a dependence occurs. We refer to this hardware as inter-lock logic. The amount and complexity of the interlock logic required to support a ten+ instruction issue bandwidth is a major concern in the design of the pipeline control hardware. We look specifically at register interlocks in the context of a parallel pipeline with separate dispatch and issue phases - a generalization of the pipeline organization implemented by a number of prominent recent superscalar processors. We describe four implementations of the register interlock logic and a comparison baaed on the number of logic levels. We al-so present a high-bandwidth implementation of table-based register renaming.
S. Weiss, "Implementation Register Interlocks in Parallel-Pipeline, Multiple Instruction Queue, Superscalar Processors", 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA), vol. 00, no. , pp. 14, 1995, doi:10.1109/HPCA.1995.386559