High-Performance Interconnects, Symposium on (2008)
Aug. 26, 2008 to Aug. 28, 2008
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/HOTI.2008.23
Several types of low power passive equalizer is proposed and optimized in this work. The equalizer topologies include T-junction, parallel R-C and series R-L structures. These structures can be inserted at driver or/and receiver side at either the chip or package level and the communication bandwidth can be improved with little overhead on power consumption. Using the area of the eye as the objective function to be maximized, we optimized these equalizers for the CPU-memory interconnection of an IBM POWER6 System with and without practical constraints on the RLCG parameter values. Our experimental results show that without employing any equalizers, the data-eye is closed for a bit-rate of 6.4 Gbps. We tried twelve different equalizer schemes and found they produce very different eye diagrams. The scheme yielding the maximum eye improves the height of the eye to more than 300 mV at a total power cost of 7.2 mW, while the scheme yielding the minimum jitter limits the jitter magnitude to 10 ps at a total power cost of 9.5 mW. We also have shown that the solution resulting from the proposed optimization approach have very small sensitivity to the tolerance of the R,L,C values and the magnitude of the coupled noise.
passive equalization, low power
Y. Zhang et al., "Low Power Passive Equalizer Design for Computer Memory Links," 2008 16th IEEE Symposium on High Performance Interconnects(HOTI), Stanford, CA, 2008, pp. 51-56.