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High-Performance Interconnects, Symposium on (2007)
Stanford, CA
Aug. 22, 2007 to Aug. 24, 2007
ISSN: 1550-4794
ISBN: 0-7695-2979-8
TABLE OF CONTENTS
Introduction
Keynotes
Tutorials

Hands-on with the NetFPGA to build a Gigabit-rate Router (PDF)

Glen Gibb , Stanford University
Nick McKeown , Stanford University
John W. Lockwood , Stanford University
Jad Naous , Stanford University
Adam Covington , Stanford University
pp. 7-10

Introduction to Programming High Performance Applications on the CELL Broadband Engine (PDF)

Alfredo Buttari , University of Tennessee at Knoxville
Jakub Kurzak , University of Tennessee at Knoxville
pp. 11

Design of Interconnection Networks (PDF)

Dennis Abts Cray , Stanford University
John Kim , Stanford University
pp. 12
Session1: On-Chip Networking

Design of a Dynamic Priority-Based Fast Path Architecture for On-Chip Interconnects (Abstract)

N. Vijaykrishnan , Pennsylvania State University, University Park, PA
Ravishankar Iyer , Intel Corporation
Chita R. Das , Pennsylvania State University, University Park, PA
Reetuparna Das , Pennsylvania State University, University Park, PA
Jongman Kim , Pennsylvania State University, University Park, PA
Dongkook Park , Pennsylvania State University, University Park, PA
Chrysostomos Nicopoulos , Pennsylvania State University, University Park, PA
pp. 15-20

Photonic NoC for DMA Communications in Chip Multiprocessors (Abstract)

Keren Bergman , Columbia University
Luca P. Carloni , Columbia University
Assaf Shacham , Columbia University
Benjamin G. Lee , Columbia University
Aleksandr Biberman , Columbia University
pp. 29-38
Session 2: Switch Architecture

Backlog Aware Low Complexity Schedulers for Input Queued Packet Switches (Abstract)

Aditya Dua , Stanford University
Hans Eberle , Sun Microsystems Laboratories
Nils Gura , Sun Microsystems Laboratories
Nicholas Bambos , Stanford University
Wladek Olesinski , Sun Microsystems Laboratories
pp. 39-46

Power Aware Management of Packet Switches (Abstract)

Daniel O?Neill , Stanford University
Nicholas Bambos , Stanford University
Benjamin Yolken , Stanford University
Lykomidis Mastroleon , Stanford University
pp. 47-53

Implementation of Dynamic Bandwidth Re-allocation in Optical Interconnects using Microring Resonators (Abstract)

Chander Kochar , University of Arizona, Tucson, AZ
Avinash Kodi , University of Arizona, Tucson, AZ
Ahmed Louri , University of Arizona, Tucson, AZ
pp. 54-64
Session 3: Support for Network Security

A Real-Time Worm Outbreak Detection System Using Shared Counters (Abstract)

Mehrdad Nourani , University of Texas at Dallas, Richardson
Miad Faezipour , University of Texas at Dallas, Richardson
Rina Panigrahy , Microsoft Research Lab
pp. 65-72

Prototyping Fast, Simple, Secure Switches for Etha (Abstract)

Jianying Luo , Stanford University
Nick McKeown , Stanford University
John Lockwood , Stanford University
Justin Pettit , Stanford University
Martin Casado , Stanford University
pp. 73-82
Session 4: Routing

A Memory-Balanced Linear Pipeline Architecture for Trie-based IP Lookup (Abstract)

Weirong Jiang , University of Southern California
Viktor K. Prasanna , University of Southern California
pp. 83-90

Building a RCP (Rate Control Protocol) Test Network (Abstract)

Glen Gibb , Stanford University
Jiang Zhu , Stanford University
Nandita Dukkipati , Stanford University
Nick McKeown , Stanford University
pp. 91-98

ElephantTrap: A low cost device for identifying large flows (Abstract)

Yi Lu , Stanford University
Flavio Bonomi , Cisco Systems
Balaji Prabhakar , Stanford University
pp. 99-108
Session 5: Performance Evaluation

An Analysis of 10-Gigabit Ethernet Protocol Stacks in Multicore Environments (Abstract)

G. Narayanaswamy , Virginia Tech
W. Feng , Virginia Tech
P. Balaji , Argonne National Laboratory
pp. 109-116

Assessing the Ability of Computation/Communication Overlap and Communication Progress in Modern Interconnects (Abstract)

Ahmad Afsahi , Queen?s University, Kingston, ON, CANADA
Mohammad J. Rashti , Queen?s University, Kingston, ON, CANADA
pp. 117-124

Performance Analysis and Evaluation of Mellanox ConnectX InfiniBand Architecture with Multi-Core Platforms (Abstract)

Lei , Ohio State University
Sayantan Sur , Ohio State University
Dhabaleswar K. Panda , Ohio State University
Matthew J. Koop , Ohio State University
pp. 125-134
Session 6: OS/Network Interface Technology

Memory Management Strategies for Data Serving with RDMA (Abstract)

Pete Wyckoff , Ohio Supercomputer Center
Dennis Dalessandro , Ohio Supercomputer Center
pp. 135-142

Reducing the Impact of the MemoryWall for I/O Using Cache Injection (Abstract)

Kurt B. Ferreira , University of New Mexico
Arthur B. Maccabe , University of New Mexico
Edgar A. Leon , University of New Mexico
pp. 143-150
Author Index

Author Index (PDF)

pp. 151
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