The Community for Technology Leaders
High-Performance Interconnects, Symposium on (2004)
Stanford, CA, USA
Aug. 5, 2004 to Aug. 7, 2004
ISBN: 0-7803-8686-8
TABLE OF CONTENTS
Keynote and Panels
Session 1: System Level Interconnects

Program Committee (Abstract)

pp. x

Performance evaluation of InfiniBand with PCI Express (Abstract)

Jiuxing Liu , Dept. of Comput. & Sci. & Eng., Ohio State Univ., Columbus, OH, USA
A. Mamidala , Dept. of Comput. & Sci. & Eng., Ohio State Univ., Columbus, OH, USA
A. Vishnu , Dept. of Comput. & Sci. & Eng., Ohio State Univ., Columbus, OH, USA
D.K. Panda , Dept. of Comput. & Sci. & Eng., Ohio State Univ., Columbus, OH, USA
pp. 13-19

Performance evaluation of the Cray X1 distributed shared memory architecture (Abstract)

D.K. Panda , Oak Ridge Nat. Lab., TN, USA
J.S. Vetter , Oak Ridge Nat. Lab., TN, USA
P.H. Worley , Oak Ridge Nat. Lab., TN, USA
pp. 20-25
Session 2: Packet Classification And Lookup

Efficient multi-match packet classification with TCAM (Abstract)

R.H. Katz , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Fang Yu , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 28-34

Non-random generator for IPv6 tables (Abstract)

Mei Wang , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
T. Hain , Oak Ridge Nat. Lab., TN, USA
L. Dunn , Dept. of Comput. & Sci. & Eng., Ohio State Univ., Columbus, OH, USA
S. Deering , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 35-40

Efficient prefix cache for network processors (Abstract)

M.J. Akhbarizadeh , Center for Integrated Circuits & Syst., Texas Univ., Richardson, TX, USA
M. Nourani , Center for Integrated Circuits & Syst., Texas Univ., Richardson, TX, USA
pp. 41-46
Session 3: Routers and Switches

Configuring a load-balanced switch in hardware (Abstract)

I. Keslassy , Oak Ridge Nat. Lab., TN, USA
N. McKeown , Dept. of Comput. & Sci. & Eng., Ohio State Univ., Columbus, OH, USA
Shang-Tse Chuang , Comput. Syst. Lab., Stanford Univ., CA, USA
S. Arekapudi , Comput. Syst. Lab., Stanford Univ., CA, USA
pp. 48-53

Designing packet buffers with statistical guarantees (Abstract)

G. Shrimali , Comput. Syst. Lab., Stanford Univ., CA, USA
I. Keslassy , Comput. Syst. Lab., Stanford Univ., CA, USA
N. McKeown , Comput. Syst. Lab., Stanford Univ., CA, USA
pp. 54-60

Efficient multicast on a terabit router (Abstract)

S.C. Krishnan , Comput. Syst. Lab., Stanford Univ., CA, USA
R. Panigrahy , Comput. Syst. Lab., Stanford Univ., CA, USA
P. Bhargava , Comput. Syst. Lab., Stanford Univ., CA, USA
pp. 61-67
Session 4: Security and Network Processors

Worms vs. perimeters: the case for hard-LANs (Abstract)

S. Staniford , Comput. Syst. Lab., Stanford Univ., CA, USA
D. Ellis , Comput. Syst. Lab., Stanford Univ., CA, USA
V. Paxson , Dept. of Comput. & Sci. & Eng., Ohio State Univ., Columbus, OH, USA
N. Weaver , Comput. Syst. Lab., Stanford Univ., CA, USA
pp. 70-76

Design of a system for real-time worm detection (Abstract)

J. Lockwood , Dept. of Comput. Sci. & Eng., Washington Univ., St. Louis, MO, USA
B. Madhusudan , Dept. of Comput. Sci. & Eng., Washington Univ., St. Louis, MO, USA
pp. 77-83

Studying network protocol offload with emulation: approach and preliminary results (Abstract)

E. Lemoine , Sun Microsystems, Inc., Santa Clara, CA, USA
K. Kunze , Sun Microsystems, Inc., Santa Clara, CA, USA
R. Westrelin , Sun Microsystems, Inc., Santa Clara, CA, USA
N. Fugier , Sun Microsystems, Inc., Santa Clara, CA, USA
E. Nordmark , Sun Microsystems, Inc., Santa Clara, CA, USA
pp. 84-90
Session 5: Architectures

Design of a high-speed optical interconnect for scalable shared memory multiprocessors (Abstract)

A.K. Kodi , Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
A. Louri , Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
pp. 92-97

Evaluation of a wireless enterprise backbone network architecture (Abstract)

Tzi-cker Chiueh , Dept. of Comput. Sci., State Univ. of New York, Stony Brook, NY, USA
A. Raniwala , Dept. of Comput. Sci., State Univ. of New York, Stony Brook, NY, USA
pp. 98-104

Copyright (Abstract)

pp. iv

Patrons (Abstract)

pp. xi

Resilient network infrastructures for global grid computing (Abstract)

L. Valcarenghi , Dept. of Comput. Sci., State Univ. of New York, Stony Brook, NY, USA
pp. 105-106

High-speed networking: a systematic approach to high-bandwidth low-latency communication (Abstract)

J. Sterbenz , Comput. Networks Res. Group, Massachusetts Univ., Amherst, MA, USA
pp. 107-108

Internet infrastructure security (Abstract)

G. Manimaran , Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA
pp. 109-108

Author Index (Abstract)

pp. 111

Message from the General Chairs (Abstract)

J.B. Lyles , Nortel Networks
A. Watters , Dept. of Comput. Sci., State Univ. of New York, Stony Brook, NY, USA
pp. vii

Message from the Program Chairs (Abstract)

J. Sterbenz , University of Massachusetts
D. Stiliadis , Dept. of Comput. Sci., State Univ. of New York, Stony Brook, NY, USA
pp. viii
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