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High-Performance Interconnects, Symposium on (2004)
Stanford, CA, USA
Aug. 5, 2004 to Aug. 7, 2004
ISBN: 0-7803-8686-8
pp: 54-60
G. Shrimali , Comput. Syst. Lab., Stanford Univ., CA, USA
I. Keslassy , Comput. Syst. Lab., Stanford Univ., CA, USA
N. McKeown , Comput. Syst. Lab., Stanford Univ., CA, USA
ABSTRACT
Packet buffers are an essential part of routers. In high-end routers, these buffers need to store a large amount of data at very high speeds. To satisfy these requirements, we need a memory with the the speed of SRAM and the density of DRAM. A typical solution is to use hybrid packet buffers built from a combination of SRAM and DRAM, where the SRAM holds the heads and tails of per-flow packet FIFOs and the DRAM is used for bulk storage. The main challenge then is to minimize the size of the SRAM while providing reasonable performance guarantees. We analyze a commonly used hybrid architecture from a statistical perspective, and investigate how small the SRAM can get if the packet buffer designer is willing to tolerate a certain drop probability. We introduce an analytical model to represent the SRAM buffer occupancy, and derive drop probabilities as a function of SRAM size under a wide range of statistical traffic patterns. By our analysis, we show that, for low drop probability, the required SRAM size is proportional to the number of flows.
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CITATION

G. Shrimali, I. Keslassy and N. McKeown, "Designing packet buffers with statistical guarantees," High-Performance Interconnects, Symposium on(HOTI), Stanford, CA, USA, 2004, pp. 54-60.
doi:10.1109/CONECT.2004.1375202
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