High-Performance Interconnects, Symposium on (2004)
Stanford, CA, USA
Aug. 5, 2004 to Aug. 7, 2004
S. Arekapudi , Comput. Syst. Lab., Stanford Univ., CA, USA
Shang-Tse Chuang , Comput. Syst. Lab., Stanford Univ., CA, USA
I. Keslassy , Oak Ridge Nat. Lab., TN, USA
N. McKeown , Dept. of Comput. & Sci. & Eng., Ohio State Univ., Columbus, OH, USA
The load-balanced switch architecture is a promising way to scale router capacity. We explained previously (Keslassy, I. et al., Proc. ACM SIGCOMM, 2003) how it can be used to build a 100 Tb/s router with no centralized scheduler, no memory operating faster than the line-rate, no packet mis-sequencing, a 100% throughput guarantee for all traffic patterns, and an optical switch fabric that simply spreads traffic evenly among linecards. This switch fabric uses optical MEMS switches that are reconfigured only when linecards are added and deleted, allowing the router to function when any subset of linecards is present and working. We have also introduced a configuration algorithm that can find a correct configuration of the MEMS switches in polynomial time (Keslassy et al., Proc. IEEE Infocom '04, 2004). However, we found that our algorithm takes over 50 seconds to run in software for a 100 Tb/s router. Our goal is to restore the router to operation within 50 ms of failure. We have modified our algorithm for implementation in dedicated hardware. In particular, to simplify the Ford-Fulkerson algorithm in bipartite matches, we reduce memory accesses and use bit manipulation schemes. Then, we decompose permutations using the Slepian-Duguid algorithm and reduce the configuration time with a simplified memory scheme. Our experimental results show that it is possible to achieve the 50 ms target.
I. Keslassy, N. McKeown, S. Chuang and S. Arekapudi, "Configuring a load-balanced switch in hardware," High-Performance Interconnects, Symposium on(HOTI), Stanford, CA, USA, 2004, pp. 48-53.