Aug. 20, 2003 to Aug. 22, 2003
Jiang Xu , Princeton University
Wayne Wolf , Princeton University
The paper describes a structured communication link design technique, wave-pipelined interconnect, for networks-on-chip. We achieved 3.45GHz and 55.2Gbps throughput on a 10mm 16bit interconnection in a 0.25um technology. It uses 0.079mm<sup>2</sup> of area, and it only needs 18.8p<sup>J</sup> to transmit one bit. We reduce 79% crosstalk delay by using two techniques -- interleaved lines and misaligned repeaters. This paper shows the various techniques we used to save power and area and achieve high performance in a relative old technology in detail. Wave-pipelined interconnect design is relatively easy, but many features of it give a large and flexible design space for high-performance chips.
Jiang Xu, Wayne Wolf, "A Wave-Pipelined On-chip Interconnect Structure for Networks-on-Chips", HOTI, 2003, High-Performance Interconnects, Symposium on, High-Performance Interconnects, Symposium on 2003, pp. 10, doi:10.1109/CONECT.2003.1231471