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2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) (2016)
McLean, VA, USA
May 3, 2016 to May 5, 2016
ISBN: 978-1-4673-8825-2
pp: 236-241
Muhammad Yasin , Electrical and Computer Engineering, NYU Tandon School of Engineering, NY, USA
Bodhisatwa Mazumdar , Electrical and Computer Engineering, New York University Abu Dhabi, Abu Dhabi, U.A.E.
Jeyavijayan J V Rajendran , Erik Jonsson School of Engineering & Computer Science, The University of Texas at Dallas, TX, USA
Ozgur Sinanoglu , Electrical and Computer Engineering, New York University Abu Dhabi, Abu Dhabi, U.A.E.
ABSTRACT
Logic locking is an Intellectual Property (IP) protection technique that thwarts IP piracy, hardware Trojans, reverse engineering, and IC overproduction. Researchers have taken multiple attempts in breaking logic locking techniques and recovering its secret key. A Boolean Satisfiability (SAT) based attack has been recently presented that breaks all the existing combinational logic locking techniques. In this paper, we develop a lightweight countermeasure against this and other attacks that aim at gradually pruning the key search space. Our proposed logic locking technique, referred to as SARLock, maximizes the required number of distinguishing input patterns to recover the secret key. SARLock thwarts the SAT attack by rendering the attack effort exponential in the number of bits in the secret key, while its overhead grows only linearly.
INDEX TERMS
Logic gates, Integrated circuits, Electronics packaging, Resistance, Foundries, Security, Benchmark testing
CITATION

M. Yasin, B. Mazumdar, J. J. Rajendran and O. Sinanoglu, "SARLock: SAT attack resistant logic locking," 2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), McLean, VA, USA, 2016, pp. 236-241.
doi:10.1109/HST.2016.7495588
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