2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) (2016)
McLean, VA, USA
May 3, 2016 to May 5, 2016
Subhadeep Banik , DTU Compute, Technical University of Denmark, 2800 Kgs. Lyngby
Andrey Bogdanov , DTU Compute, Technical University of Denmark, 2800 Kgs. Lyngby
Kazuhiko Minematsu , NEC Corporation, Kawasaki, Japan
The most compact implementation of the AES-128 algorithm was the 8-bit serial circuit proposed in the work of Moradi et. al. (Eurocrypt 2011). The circuit has an 8-bit datapath and occupies area equivalent to around 2400 GE. Since many authenticated encryption modes use the AES-128 algorithm as the underlying block cipher, we investigate if they can be implemented in a compact fashion using the 8-bit serialized AES circuit. In this context we investigate three authenticated encryption modes CLOC, SILC and AES-OTR. Using the standard cell library of the STM 90nm process, we implemented CLOC and SILC with around 3110 GE whereas AES-OTR was implemented with around 4720 GE.
Registers, Encryption, Logic gates, Multiplexing, Ciphers, Computer architecture, Hardware
S. Banik, A. Bogdanov and K. Minematsu, "Low-area hardware implementations of CLOC, SILC and AES-OTR," 2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), McLean, VA, USA, 2016, pp. 71-74.