2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) (2016)
McLean, VA, USA
May 3, 2016 to May 5, 2016
Sikhar Patranabis , Department of Computer Science and Engineering, IIT Kharagpur, India
Debapriya Basu Roy , Department of Computer Science and Engineering, IIT Kharagpur, India
Yash Shrivastava , Department of Computer Science and Engineering, IIT Kharagpur, India
Debdeep Mukhopadhyay , Department of Computer Science and Engineering, IIT Kharagpur, India
Santosh Ghosh , Intel Labs, Hillsboro, Oregon, USA
Linear layers are crucial building blocks in the design of lightweight block ciphers, since they perform the dual task of providing the much needed diffusion, while also ensuring minimal hardware cost for implementation. Although a number of lightweight block ciphers with parsimoniously designed linear layers have been proposed in cryptographic literature, there is limited work on generic construction techniques for such linear layers, to the best of our knowledge. The challenge in designing a suitable linear layer, that combines the requirements of both cryptographic strength and lightweightedness, lies in the huge search space accompanying such a construction technique. In this paper, we propose a hierarchical linear layer construction technique that systematically combines the principles of block interleaving and wide trail design strategy to construct large linear layers from suitably chosen smaller linear layers that guarantee the necessary diffusion properties. Additionally, the smaller linear layers are realized by iterating linear layers which are extremely lightweight, thus providing us with a strategy to guarantee diffusion while ensuring that the gate count of the design is minimized. In order to demonstrate the efficiency of our proposed technique, we compare it with the general construction technique proposed for the design of the block cipher PRIDE. To the best of our knowledge, PRIDE offers the only other general construction technique that focuses specifically on the construction of lightweight linear layers. While the construction technique of PRIDE is efficient for software implementations, our technique provides 60% and 50% greater savings in terms of area footprint on ASIC and FPGA based designs respectively, with an overall area-time product reduction by 7.5%. The main contribution of this work lies in providing the cipher design community with a generic off-the-shelf technique for designing lightweight linear layers with high diffusion for hardware-oriented applications.
Ciphers, Hardware, Logic gates, Generators, Measurement
S. Patranabis, D. B. Roy, Y. Shrivastava, D. Mukhopadhyay and S. Ghosh, "Parsimonious design strategy for linear layers with high diffusion in block ciphers," 2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), McLean, VA, USA, 2016, pp. 31-36.