The Community for Technology Leaders
2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) (2014)
Arlington, VA, USA
May 6, 2014 to May 7, 2014
ISBN: 978-1-4799-4114-8
pp: 130-135
Loic Zussa , Ecole Nationale Superieure des Mines de Saint-Etienne (ENSM.SE), Gardanne, France
Jean-Max Dutertre , Ecole Nationale Superieure des Mines de Saint-Etienne (ENSM.SE), Gardanne, France
Jessy Clediere , Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA), Gardanne/Grenoble, France
Bruno Robisson , Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA), Gardanne/Grenoble, France
ABSTRACT
Power supply underpowering and negative power supply glitches are commonly used for the purpose of injecting faults into secure circuits. The related fault injection mechanism has been extensively studied: it is based on setup time violations. Positive power supply glitches are also used to inject faults. However, an increase of the supply voltage is not consistent with a mechanism based on setup time violation. Besides, no research work has yet identified the corresponding mechanism. In this work, we report the use of an embedded delay-meter to monitor the core voltage of a programmable device exposed to power supply glitches. It permitted us to gain a further insight into the mechanism associated with power glitches and also to identify the injection mechanism of positive power supply glitches.
INDEX TERMS
Clocks,
CITATION

L. Zussa, J. Dutertre, J. Clediere and B. Robisson, "Analysis of the fault injection mechanism related to negative and positive power supply glitches using an on-chip voltmeter," 2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), Arlington, VA, USA, 2014, pp. 130-135.
doi:10.1109/HST.2014.6855583
86 ms
(Ver 3.3 (11022016))