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2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) (2014)
Arlington, VA, USA
May 6, 2014 to May 7, 2014
ISBN: 978-1-4799-4114-8
pp: 64-69
Dylan Ismari , University of New Mexico, USA
Jim Plusquellic , University of New Mexico, USA
ABSTRACT
A complete on-chip implementation of a bit generation engine using a physical unclonable function is presented in this paper. The bit generation engine, called the JellyFishPUF (JFP), provides keying material for encryption, authentication bitstrings for anti-counterfeiting and true random number generation. JFP utilizes a Physical Unclonable Function that is based on resistance variations in metals and transistors. JFP is fully implemented as a layout in an area of 0.125 mm2 using a 65 nm technology, which includes a 2KB SRAM for public data storage. The bitstrings produced from Monte Carlo SPICE-level simulations of the entropy source in combination with logic simulations of the digital engine are evaluated with respect to randomness, uniqueness and stability metrics across a wide range of temperature and voltage corners.
INDEX TERMS
Entropy, Engines, Wires, Arrays, Delays, Metals, Authentication
CITATION

D. Ismari and J. Plusquellic, "IP-level implementation of a resistance-based physical unclonable function," 2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), Arlington, VA, USA, 2014, pp. 64-69.
doi:10.1109/HST.2014.6855570
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