2016 IEEE International High Level Design Validation and Test Workshop (HLDVT) (2016)
Santa Cruz, CA, USA
Oct. 7, 2016 to Oct. 8, 2016
Prachi Joshi , Virginia Tech, USA
Vedahari Narasimhan G. , Virginia Tech, USA
Haibo Zeng , Virginia Tech, USA
Sandeep K. Shukla , IIT Kanpur, India
Chung-wei Lin , Toyota InfoTech. Center, USA
Huafeng Yu , Boeing Research and Technology, USA
Time Triggered Ethernet (TTE) is a time-triggered network technology with large bandwidth and services for deterministic, safety-relevant commnnication. Hence, it has gained increasing attention from domains such as aerospace, automotive and industrial applications. In this work, we aim to solve the problem of task mapping and commuuication scheduling in automotive design. The system model is a dataflow task commnnication model mapped to a target architecture based on TIE. The design variables are the mapping of tasks onto the end systems in the architedure and the scheduling of all frames. The constraints include the schedulability of tasks and signals, as well as the latency constraints of the critical paths as spedfied by the designer. It can be shown that the problem is NP· hard. Therefore, we develop a heuristic to solve this problem. The heuristic contains four steps and all of them (except scheduling) are formulated using Integer Linear Programming (ILP). We present experimental results on an industrial benchmark and two synthetic benchmarks which show the efficiency and scalability of our approach.
Time-triggered Ethernet, Design space exploration, Mapping and scheduling
P. Joshi, V. N. G., H. Zeng, S. K. Shukla, C. Lin and H. Yu, "Design space exploration for deterministic ethernet-based architecture of automotive systems," 2016 IEEE International High Level Design Validation and Test Workshop (HLDVT), Santa Cruz, CA, USA, 2016, pp. 53-61.