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2012 IEEE International High Level Design Validation and Test Workshop (HLDVT) (2012)
Huntington Beach, CA, USA USA
Nov. 9, 2012 to Nov. 10, 2012
ISSN: 1552-6674
ISBN: 978-1-4673-2897-5
TABLE OF CONTENTS
Papers

Author index (PDF)

pp. 1-3

Accelerating SystemC simulations using GPUs (PDF)

Mahesh Nanjundappa , Department of Electrical and Computer Engineering, Virginia Tech., Blacksburg, Virginia, 24060, USA
Anirudh Kaushik , Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, Ontario, N2L 3G1, Canada
Hiren D. Patel , Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, Ontario, N2L 3G1, Canada
Sandeep K. Shukla , Department of Electrical and Computer Engineering, Virginia Tech., Blacksburg, Virginia, 24060, USA
pp. 132-139

Eliminating race conditions in system-level models by using parallel simulation infrastructure (PDF)

Weiwei Chen , Center for Embedded Computer Systems, University of California, Irvine, USA
Che-Wei Chang , Center for Embedded Computer Systems, University of California, Irvine, USA
Xu Han , Center for Embedded Computer Systems, University of California, Irvine, USA
Rainer Domer , Center for Embedded Computer Systems, University of California, Irvine, USA
pp. 118-123

Accurate profiling of oracles for self-checking time-constrained embedded software (PDF)

Simone Bronuzzi , University of Verona Strada Le Grazie 15, Verona, Italy
Giuseppe Di Guglielmo , University of Verona Strada Le Grazie 15, Verona, Italy
Franco Fummi , University of Verona Strada Le Grazie 15, Verona, Italy
Graziano Pravadelli , University of Verona Strada Le Grazie 15, Verona, Italy
pp. 96-99

Emulation in post-silicon validation: It's not just for functionality anymore (PDF)

Kyle Balston , Dept. of Electrical and Computer Engineering, University of British Columbia, Canada
Alan J. Hu , Dept. of Computer Science, University of British Columbia, Canada
Steven J. E. Wilton , Dept. of Electrical and Computer Engineering, University of British Columbia, Canada
Amir Nahir , IBM Research, Israel
pp. 110-117

On-chip stimuli generation for post-silicon validation (PDF)

Nicola Nicolici , Department of Electrical and Computer Engineering, McMaster University, Hamilton, ON, L8S 4K1, Canada
pp. 108-109

Post-silicon verification and debugging with control flow traces and patchable hardware (PDF)

Masahiro Fujita , VLSI Design and Education Center (VDEC) University of Tokyo
pp. 100-107

Embedded system verification through constraint-based scheduling (PDF)

Olfat El-Mahi , Department of Computer and Software Engineering École Polytechnique de Montréal, Québec, Canada
Gabriela Nicolescu , Department of Computer and Software Engineering École Polytechnique de Montréal, Québec, Canada
Gilles Pesant , Department of Computer and Software Engineering École Polytechnique de Montréal, Québec, Canada
Giovanni Beltrame , Department of Computer and Software Engineering École Polytechnique de Montréal, Québec, Canada
pp. 92-95

Monitoring distributed reactive systems (PDF)

Yu Bai , Embedded Systems Group, Department of Computer Science, University of Kaiserslautern, Germany
Jens Brandt , Embedded Systems Group, Department of Computer Science, University of Kaiserslautern, Germany
Klaus Schneider , Embedded Systems Group, Department of Computer Science, University of Kaiserslautern, Germany
pp. 84-91

A formal method to improve SystemVerilog functional coverage (PDF)

An-Che Cheng , Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan
Chia-Chih Yen , Logic Verification Group SpringSoft Inc. Hsinchu, Taiwan
Jing-Yang Jou , Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan
pp. 56-63

The strange pair: IP-XACT and univerCM to integrate heterogeneous embedded systems (PDF)

Diego Braga , Department of Computer Science - University of Verona, Verona, Italy
Franco Fummi , Department of Computer Science - University of Verona, Verona, Italy
Graziano Pravadelli , Department of Computer Science - University of Verona, Verona, Italy
Sara Vinco , Department of Computer Science - University of Verona, Verona, Italy
pp. 76-83

Constrained signal selection for post-silicon validation (PDF)

Kanad Basu , Computer and Information Science and Engineering, University of Florida, Gainesville, USA
Prabhat Mishra , Computer and Information Science and Engineering, University of Florida, Gainesville, USA
Priyadarsan Patra , Post-Si Validation Architecture Intel Corporation, USA
pp. 71-75

A functional test generation technique for RTL datapaths (PDF)

Bijan Alizadeh , School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Iran
Masahiro Fujita , VLSI Design and Education Center (VDEC), University of Tokyo and CREST, Japan
pp. 64-70

Using haloes in mixed-signal assertion based verification (PDF)

Dogan Ulus , Department of Electrical and Electronics Engineering, Bogazici University, Istanbul, Turkey
Alper Sen , Department of Computer Engineering, Bogazici University, Istanbul, Turkey
pp. 49-55

Single-source hardware modeling of different abstraction levels with State Charts (PDF)

Rainer Findenig , Upper Austrian University of Applied Sciences, Hagenberg, Austria
Thomas Leitner , DMCE GmbH & Co KG, Linz, Austria
Wolfgang Ecker , Infineon Technologies AG, Neubiberg, Germany
pp. 41-48

Behavior Driven Development for circuit design and verification (PDF)

Melanie Diepenbeck , Institute of Computer Science, University of Bremen, 28359 Bremen, Germany
Mathias Soeken , Institute of Computer Science, University of Bremen, 28359 Bremen, Germany
Daniel Grose , Institute of Computer Science, University of Bremen, 28359 Bremen, Germany
Rolf Drechsler , Institute of Computer Science, University of Bremen, 28359 Bremen, Germany
pp. 9-16

Automatic generation of Verilog bus transactors from natural language protocol specifications (PDF)

Ian G. Harris , Center for Embedded Computer Systems, University of California Irvine
pp. 33-40

Automatic generation of deadlock detection algorithms for a family of microarchitecture description languages of communication fabrics (PDF)

Freek Verbeek , Radboud University Nijmegen Institute for Computing and Information Sciences PO Box 9010 6500GL Nijmegen, The Netherlands
Julien Schmaltz , Open University of the Netherlands School of Computer Science PO Box 2960 6401DL Heerlen, The Netherlands
pp. 25-32

Using decision diagrams to compactly represent the state space for explicit model checking (PDF)

Hao Zheng , Dept. of Computer Science and Engineering at the University of South Florida, Tampa, FL
Andrew Price , Dept. of Computer Science and Engineering at the University of South Florida, Tampa, FL
Chris Myers , Dept. of Electrical and Computer Engineering at the University of Utah, SLC, UT
pp. 17-24

Sequential equivalence checking of hard instances with targeted inductive invariants and efficient filtering strategies (PDF)

Huy Nguyen , Bradley Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, VA 24061, USA
Michael S. Hsiao , Bradley Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, VA 24061, USA
pp. 1-8
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