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2012 IEEE International High Level Design Validation and Test Workshop (HLDVT) (2012)
Huntington Beach, CA, USA USA
Nov. 9, 2012 to Nov. 10, 2012
ISSN: 1552-6674
ISBN: 978-1-4673-2897-5
pp: 132-139
Mahesh Nanjundappa , Department of Electrical and Computer Engineering, Virginia Tech., Blacksburg, Virginia, 24060, USA
Anirudh Kaushik , Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, Ontario, N2L 3G1, Canada
Hiren D. Patel , Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, Ontario, N2L 3G1, Canada
Sandeep K. Shukla , Department of Electrical and Computer Engineering, Virginia Tech., Blacksburg, Virginia, 24060, USA
ABSTRACT
Recent developments in graphics processing unit (GPU) technology has invigorated an interest in using GPUs for accelerating the simulation of SystemC models. SystemC is extensively used for design space exploration, and early performance analysis of hardware systems. SystemC's reference implementation of the simulation kernel supports a single-threaded simulation kernel. However, modern computing platforms offer substantially more compute power by means of multiple central processing units, and multiple co-processors such as GPUs. This has peaked an interest in parallelizing SystemC simulations. Of these, several efforts focus on utilizing the massive parallelism offered by GPUs as an alternate computing platform. In this paper, we present a summary of these recent research efforts that propose using GPUs for accelerating SystemC simulation.
INDEX TERMS
Discrete-event Simulation, SystemC, GPUs, GPGPU
CITATION

M. Nanjundappa, A. Kaushik, H. D. Patel and S. K. Shukla, "Accelerating SystemC simulations using GPUs," 2012 IEEE International High Level Design Validation and Test Workshop (HLDVT), Huntington Beach, CA, USA USA, 2012, pp. 132-139.
doi:10.1109/HLDVT.2012.6418255
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