The Community for Technology Leaders
2012 IEEE International High Level Design Validation and Test Workshop (HLDVT) (2011)
Napa Valley, CA, USA
Nov. 9, 2011 to Nov. 11, 2011
ISBN: 978-1-4577-1744-4
TABLE OF CONTENTS
Papers

Author index (PDF)

pp. 1-3

Sufficiency-based filtering of invariants for Sequential Equivalence Checking (Abstract)

Michael S. Hsiao , Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, Virginia, USA
Wei Hu , Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, Virginia, USA
Huy Nguyen , Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, Virginia, USA
pp. 1-8

Modular equivalence verification of polynomial datapaths with multiple word-length operands (Abstract)

Masahiro Fujita , VLSI Design and Education Center (VDEC), University of Tokyo and CREST, Japan
Bijan Alizadeh , Electrical and Computer Engineering Department, University of Tehran, Iran
pp. 9-16

Using SystemVerilog assertions to relate non-cycle-accurate to cycle-accurate designs (Abstract)

Tobias Dornes , Computer Systems Group, Technische Universität Darmstadt, Germany
Hans Eveking , Computer Systems Group, Technische Universität Darmstadt, Germany
Martin Schweikert , Computer Systems Group, Technische Universität Darmstadt, Germany
pp. 17-24

Using SystemVerilog assertions to relate non-cycle-accurate to cycle-accurate designs (Abstract)

Hans Eveking , Computer Systems Group, Technische Universitat Darmstadt, Germany
Tobias Dornes , Computer Systems Group, Technische Universitat Darmstadt, Germany
Martin Schweikert , Computer Systems Group, Technische Universitat Darmstadt, Germany
pp. 17-24
Papers

UNIVERCM: The UNIversal VERsatile computational model for heterogeneous embedded system design (Abstract)

Luigi Di Guglielm , Department of Computer Science - University of Verona, Verona, Italy
Franco Fummi , Department of Computer Science - University of Verona, Verona, Italy
Francesco Stefanni , Department of Computer Science - University of Verona, Verona, Italy
Sara Vinco , Department of Computer Science - University of Verona, Verona, Italy
Graziano Pravadelli , Department of Computer Science - University of Verona, Verona, Italy
pp. 33-40

A scalable hybrid verification system based on HDL slicing (Abstract)

Saurabh Jain , Mentor Graphics Pvt. Ltd., India
Tushar Gupta , Mentor Graphics Pvt. Ltd., India
Somnath Banerjee , Mentor Graphics Pvt. Ltd., India
pp. 41-48

Coverage discounting: A generalized approach for testbench qualification (Abstract)

P. Lisherness , Univ. of California, Santa Barbara, Santa Barbara, CA, USA
Kwang-Ting Cheng , Univ. of California, Santa Barbara, Santa Barbara, CA, USA
pp. 49-56
Papers

IP-XACT based system level mutation testing (Abstract)

Florian Letombe , SpringSoft Inc. Moirans, France
Tao Xie , University of Paderborn /C-LAB, Paderborn, Germany
Wolfgang Mueller , University of Paderborn /C-LAB, Paderborn, Germany
pp. 65-71

Automatic generation of transducer models for multicore system design (Abstract)

Samar Abdi , Department of Electrical and Computer Engineering, Concordia University, Montreal, Canada
Hansu Cho , Design Solution Lab. DMC R&D Center, Samsung Electronics, Suwon-City, Korea
pp. 72-79

Interactive presentation abstract: Assertion-based verification in embedded-software design (Abstract)

Giuseppe Di Guglielmo , University of Verona - Department of Computer Science, Italy
Luigi Di Guglielmo , University of Verona - Department of Computer Science, Italy
Graziano Pravadelli , University of Verona - Department of Computer Science, Italy
Franco Fummi , University of Verona - Department of Computer Science, Italy
pp. 80

Interactive presentation abstract: Reusing of properties after discretization of hybrid automata (Abstract)

Franco Fummi , Dipartimento di Informatica - Università di Verona
Graziano Pravadelli , Dipartimento di Informatica - Università di Verona
Luigi Di Guglielmo , Dipartimento di Informatica - Università di Verona
pp. 81

Analog transaction level modeling (Abstract)

Alexander W. Rath , Infineon Technologies AG, 85579 Neubiberg, Germany, Technische Universität München
Wolfgang Ecker , Infineon Technologies AG, 85579 Neubiberg, Germany, Technische Universität München
Volkan Esen , Infineon Technologies AG
pp. 82

Interactive presentation abstract: Automated correction of design errors by edge redirection on high-level decision diagrams (Abstract)

Jaan Raik , Tallinn University of Technology, Estonia
Raimund Ubar , Tallinn University of Technology, Estonia
Anton Karputkin , Tallinn University of Technology, Estonia
Mati Tombak , Tallinn University of Technology, Estonia
pp. 83

SAT-based techniques for determining backbones for post-silicon fault localisation (Abstract)

Divjyot Sethi , Department of Electrical Engineering, Princeton University
Sharad Malik , Department of Electrical Engineering, Princeton University
Charlie Shucheng Zhu , Department of Electrical Engineering, Princeton University
Georg Weissenbacher , Department of Electrical Engineering, Princeton University
pp. 84-91

Post-silicon code coverage evaluation with reduced area overhead for functional verification of SoC (Abstract)

Alan J. Hu , Dept. of Computer Science, University of British Columbia
Andre Ivanov , Dept. of Electrical and Computer Engineering, University of British Columbia
Kyle Balston , Dept. of Electrical and Computer Engineering, University of British Columbia
Mehdi Karimibiuki , Dept. of Electrical and Computer Engineering, University of British Columbia
pp. 92-97

Modeling, synthesis, and validation of heterogeneous biomedical embedded systems (Abstract)

Gunar Schirner , Department of Electrical and Computer Engineering, College of Engineering, Northeastern University, Boston, Massachusetts 02115
pp. 106-109

Towards scalable utilization of embedded manycores in throughput-sensitive applications (Abstract)

Matin Hashemi , University of California, Davis, Department of Electrical and Computer Engineering, Davis, CA 95616
Soheil Ghiasi , University of California, Davis, Department of Electrical and Computer Engineering, Davis, CA 95616
pp. 110-115

Software agnostic approaches to explore pre-silicon system performance (Abstract)

Kenneth J. Schultz , Platform Development - Modeling, Research In Motion Limited, Waterloo, Canada
Frederic Risacher , Platform Development - Modeling, Research In Motion Limited, Waterloo, Canada
pp. 116-120

Formal verification guided automatic design error diagnosis and correction of complex processors (Abstract)

Amir Masoud Gharehbaghi , VLSI Design and Education Center, University of Tokyo and CREST, Japan Science and Technology, Tokyo, Japan
Masahiro Fujita , VLSI Design and Education Center, University of Tokyo and CREST, Japan Science and Technology, Tokyo, Japan
pp. 121-127

Utilizing GPGPUs for design validation with a modified Ant Colony Optimization (Abstract)

Michael S. Hsiao , Bradley Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, VA 24061, USA
Min Li , Bradley Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, VA 24061, USA
Kelson Gent , Bradley Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, VA 24061, USA
pp. 128-135

Verification of composite Galois field multipliers over GF ((2 (Abstract)

Florian Enescu , Department of Mathematics and Statistics Georgia State University, Atlanta, GA 30302-4038
Jinpeng Lv , Department of Electrical and Computer Eng. University of Utah, Salt Lake City, UT-84112
Priyank Kalla , Department of Electrical and Computer Eng. University of Utah, Salt Lake City, UT-84112
pp. 136-143
97 ms
(Ver 3.3 (11022016))