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2012 IEEE International High Level Design Validation and Test Workshop (HLDVT) (2010)
Anaheim, FL, USA
June 10, 2010 to June 12, 2010
ISBN: 978-1-4244-7805-7
TABLE OF CONTENTS
Papers

Author index (PDF)

pp. 1-3

Obtaining consistent global state dumps to interactively debug systems on chip with multiple clocks (Abstract)

Kees Goossens , Eindhoven University of Technology
Bart Vermeulen , Central R&D, NXP Semiconductors
pp. 1-8

System level simulation guided approach to improve the efficacy of clock-gating (Abstract)

Wei Zhang , Cebatech Inc., Eatontown, NJ, 07724
Sandeep K. Shukla , FERMAT Lab, Virginia Tech, Blacksburg, VA 24061
Sumit Ahuja , FERMAT Lab, Virginia Tech, Blacksburg, VA 24061
pp. 9-16

State space reductions for scalable verification of asynchronous designs (Abstract)

Haiqiong Yao , CSE dept. of the University of South Florida, Tampa, FL 33620
Chris J. Myers , ECE dept. of the University of Utah
Hao Zheng , CSE dept. of the University of South Florida, Tampa, FL 33620
pp. 17-24

Analysis of range and precision for fixed-point linear arithmetic circuits with feedbacks (Abstract)

K. Radecka , Department of Electrical and Computer Engineering McGill University, Montreal, Quebec, Canada H3A-2A7
Y. Pang , Department of Electrical and Computer Engineering McGill University, Montreal, Quebec, Canada H3A-2A7
O. Sarbishei , Department of Electrical and Computer Engineering McGill University, Montreal, Quebec, Canada H3A-2A7
pp. 25-32

Retiming arithmetic datapaths using Timed Taylor Expansion Diagrams (Abstract)

Maciej Ciesielski , University of Massachusetts Amherst, USA
Daniel Gomez-Prado , University of Massachusetts Amherst, USA
Dusung Kim , University of Massachusetts Amherst, USA
Emmanuel Boutillon , Lab-STICC, Universite¿ de Bretagne Sud, France
pp. 33-39

HIFSuite: Tools for HDL code conversion and manipulation (Abstract)

Luigi Di Guglielmo , ESD Group Department of Computer Science University of Verona, Italy
Graziano Pravadelli , ESD Group Department of Computer Science University of Verona, Italy
Alessandro Venturelli , EDALab s.r.l. Strada Le Grazie 15, 37134 Verona, Italy
Francesco Stefanni , ESD Group Department of Computer Science University of Verona, Italy
Giuseppe Di Guglielmo , ESD Group Department of Computer Science University of Verona, Italy
Nicola Bombieri , ESD Group Department of Computer Science University of Verona, Italy
Michele Ferrari , EDALab s.r.l. Strada Le Grazie 15, 37134 Verona, Italy
Franco Fummi , ESD Group Department of Computer Science University of Verona, Italy
pp. 40-41

Quick formal modeling of communication fabrics to enable verification (Abstract)

Umit Y. Ogras , Intel Corporation
Michael Kishinevsky , Intel Corporation
Satrajit Chatterjee , Intel Corporation
pp. 42-49

An improvement in decomposed reachability analysis for symbolic model checking (Abstract)

Nicholas Donataccio , University of South Florida, Tampa, Florida
Hao Zheng , University of South Florida, Tampa, Florida
pp. 50-57

Semi-formal functional verification by EFSM traversing via NuSMV (Abstract)

Graziano Pravadelli , University of Verona, Italy Department of Computer Science
Marco Roveri , Fondazione Bruno Kessler Ist. to Ricerca Scientifica e Tecnologica
Stefano Soffia , University of Verona, Italy Department of Computer Science
Franco Fummi , University of Verona, Italy Department of Computer Science
Giuseppe Di Guglielmo , University of Verona, Italy Department of Computer Science
pp. 58-65

Clock domain verification challenges and scalable solutions (Abstract)

Pranav Ashar , Real Intent Inc., Sunnyvale, California
pp. 66

Towards analyzing functional coverage in SystemC TLM property checking (Abstract)

Rolf Drechsler , Institute of Computer Science, University of Bremen, 28359 Bremen, Germany
Daniel Grose , Institute of Computer Science, University of Bremen, 28359 Bremen, Germany
Hoang M. Le , Institute of Computer Science, University of Bremen, 28359 Bremen, Germany
pp. 67-74
Papers

Static analysis of deadends in SVA constraints (Abstract)

Ashvin Dsouza , Synopsys, Inc 377 Simarano Drive Marlboro, MA 01752
pp. 82-89

A case study of Time-Multiplexed Assertion Checking for post-silicon debugging (Abstract)

Ming Gao , Dept. of Electr. & Comput. Eng., Univ. of California, Santa Barbara, Santa Barbara, CA, USA
Kwang-Ting Cheng , Dept. of Electr. & Comput. Eng., Univ. of California, Santa Barbara, Santa Barbara, CA, USA
pp. 90-96
Papers

Automatic generation of host-compiled timed TLMs for high level design (Abstract)

Samar Abdi , Department of Electrical and Computer Engineering Concordia University Montreal, Canada
pp. 103-104

Automatic synthesis of OSCI TLM-2.0 models into RTL bus-based IPs (Abstract)

Nicola Bombieri , Department of Computer Science University of Verona
Franco Fummi , Department of Computer Science University of Verona
Valerio Guarnieri , Department of Computer Science University of Verona
pp. 105-112

Automated synthesis of EDACs for FLASH memories with user-selectable correction capability (Abstract)

Maurizio Caramia , Thales Alenia Space Italia Command Control&Data Handling
Andrea Miele , Politecnico di Torino Dipartimento di Automatica ed Informatica (DAUIN)
Michele Fabiano , Politecnico di Torino Dipartimento di Automatica ed Informatica (DAUIN)
Paolo Prinetto , Politecnico di Torino Dipartimento di Automatica ed Informatica (DAUIN)
Roberto Piazza , Politecnico di Torino Dipartimento di Automatica ed Informatica (DAUIN)
pp. 113-120

Utility of transaction-level hardware models in refinement checking (Abstract)

Yogesh Mahajan , Department of EE, Princeton University, Princeton, NJ 08544, USA
Sharad Malik , Department of EE, Princeton University, Princeton, NJ 08544, USA
pp. 121-128

An ontology and constraint based approach to cache preloading (Abstract)

Gil Shurek , IBM Research labs in Haifa, Israel
Eyal Bin , IBM Research labs in Haifa, Israel
Eitan Marcus , IBM Research labs in Haifa, Israel
Rajiv Bhatia , IBM Systems and Technology Group Austin, Texas
pp. 129-136

ESL flows are enabled by high-level synthesis with universality (Abstract)

Rishiyur S. Nikhil , Bluespec, Inc. 14 Spring Street, Waltham, MA 02451
pp. 137

The relationship of code coverage metrics on high-level and RTL code (Abstract)

Eugene Zhang , Jeda Technologies, Santa Clara, CA
John Sanguinetti , Forte Design Systems San Jose, CA
pp. 138-141

ESL design and multi-core validation using the System-on-Chip Environment (Abstract)

Rainer Domer , Center for Embedded Computer Systems University of California, Irvine, USA
Weiwei Chen , Center for Embedded Computer Systems University of California, Irvine, USA
Xu Han , Center for Embedded Computer Systems University of California, Irvine, USA
pp. 142-147
Papers

Verification of real-time properties for Hardware-dependent Software (Abstract)

Markus Becker , University of Paderborn/C-LAB, Paderborn, Germany
Henning Zabel , University of Paderborn/C-LAB, Paderborn, Germany
Wolfgang Mueller , University of Paderborn/C-LAB, Paderborn, Germany
Marcio F. da S. Oliveira , University of Paderborn/C-LAB, Paderborn, Germany
pp. 154-159
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