2010 IEEE International High Level Design Validation and Test Workshop (HLDVT) (2010)
Anaheim, FL, USA
June 10, 2010 to June 12, 2010
Bart Vermeulen , Central R&D, NXP Semiconductors
Kees Goossens , Eindhoven University of Technology
Post-silicon debugging of a system on chip (SOC) is complex due to (1) the intrinsic limits on the internal observability, (2) the absence of a single global clock, and (3) the need for asynchronous intellectual property (IP) blocks to interact with each other. These aspects prevent the instantaneous capture of a complete and consistent state of the SOC, and make the SOC non-deterministic at both the clock cycle level and the behavioral level. To debug an embedded system when the states that are extracted are irreproducible and inconsistent is nearly impossible. In this paper, we therefore introduce a method to capture a consistent, complete state of a multiple-clock SOC for interactive debugging. We reuse the same functionality that is used to ensure correct functional communication between asynchronous IP blocks, namely the handshake signals common in on-chip communication protocols. We merge the required on-chip hardware to support this debug functionality with the traditional debug architecture that reuses the manufacturing scan chains for debug. Our experimental results show that it is possible to ensure a globally consistent state is observed when the system is stopped on a breakpoint event.
K. Goossens and B. Vermeulen, "Obtaining consistent global state dumps to interactively debug systems on chip with multiple clocks," 2010 IEEE International High Level Design Validation and Test Workshop (HLDVT), Anaheim, FL, USA, 2010, pp. 1-8.