The Community for Technology Leaders
2009 IEEE International High Level Design Validation and Test Workshop (2009)
San Francisco, CA USA
Nov. 4, 2009 to Nov. 6, 2009
ISSN: 1552-6674
TABLE OF CONTENTS

Analysis of scheduled Latency insensitive systems with periodic clock calculus (PDF)

Bin Xue , FERMAT Lab, ECE Dept., Virginia Polytechnic Institute and State University, Blacksburg, 24061, USA
Sandeep K. Shukla , FERMAT Lab, ECE Dept., Virginia Polytechnic Institute and State University, Blacksburg, 24061, USA
pp. 1-7

FLARE: A design environment for FLASH-based space applications (PDF)

Maurizio Caramia , Thales Alenia Space Italia, Torino, Italy
Stefano Di Carlo , Politecnico di Torino, Dipartimento di Automatica e Informatica, Italy
Michele Fabiano , Politecnico di Torino, Dipartimento di Automatica e Informatica, Italy
Paolo Prinetto , Politecnico di Torino, Dipartimento di Automatica e Informatica, Italy
pp. 14-19

MCBCG: Model Checking Based Sequential Clock-Gating (PDF)

Sumit Ahuja , CESCA, Virginia Tech, Blacksburg, 24061, USA
Sandeep Shukla , CESCA, Virginia Tech, Blacksburg, 24061, USA
pp. 20-25

Automated debugging with high level abstraction and refinement (PDF)

Sean Safarpour , Vennsa Technologies Inc., Toronto, ON M5V 3B1, USA
Andreas Veneris , University of Toronto, ECE Department, ON M5S 3G4, USA
pp. 26-31

STAR: Generating input vectors for design validation by static analysis of RTL (PDF)

Lingyi Liu , Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, USA
Shabha Vasudevan , Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, USA
pp. 32-37

Learning from constraints for formal property checking (PDF)

In-Ho Moon , Synopsys Inc., USA
Kevin Harer , Synopsys Inc., USA
pp. 38-45

Exploiting incrementality in SAT-based search for multiple equivalence-preserving transformations in combinational circuits (PDF)

Gianpiero Cabodi , Dipartimento di Automatica ed Informatica, Politecnico di Torino, Italy
Leandro Dipietro , Dipartimento di Automatica ed Informatica, Politecnico di Torino, Italy
Marco Murciano , Dipartimento di Automatica ed Informatica, Politecnico di Torino, Italy
Sergio Nocco , Dipartimento di Automatica ed Informatica, Politecnico di Torino, Italy
pp. 46-53

PowerRanger: Assessing circuit vulnerability to power attacks using SAT-based static analysis (PDF)

Jeff Hao , Department of Computer Science and Engineering, University of Michigan, Ann Arbor, United States of America
Valeria Bertacco , Department of Computer Science and Engineering, University of Michigan, Ann Arbor, United States of America
pp. 54-59

Fault table generation using Graphics Processing Units (PDF)

Kanupriya Gulati , Department of ECE, Texas A&M University, College Station TX 77843, USA
Sunil P Khatri , Department of ECE, Texas A&M University, College Station TX 77843, USA
pp. 60-67

Diagnostic Test Generation for silicon diagnosis with an incremental learning framework based on search state compatibility (PDF)

Maheshwar Chandrasekar , Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, 24061, USA
Michael S. Hsiao , Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, 24061, USA
pp. 68-75

TG-PRO: A new model for SAT-based ATPG (PDF)

Huan Chen , CASL/CSI, University College Dublin, Ireland
Joao Marques-Silva , CASL/CSI, University College Dublin, Ireland
pp. 76-81

Localizing transient faults using dynamic bayesian networks (PDF)

Susmit Jha , Department of Electrical Engineering and Computer Science, UC Berkeley, USA
Wenchao Li , Department of Electrical Engineering and Computer Science, UC Berkeley, USA
Sanjit A. Seshia , Department of Electrical Engineering and Computer Science, UC Berkeley, USA
pp. 82-87

An instrumented observability coverage method for system validation (PDF)

Peter Lisherness , ECE Department, University of California, Santa Barbara, USA
Kwang-Ting Cheng , ECE Department, University of California, Santa Barbara, USA
pp. 88-93

A symbolic execution framework for algorithm-level modelling (PDF)

Ziyad Hanna , Oxford University Computing Laboratory, Wolfson Building, Parks Road, OX1 3QD, England
Tom Melham , Oxford University Computing Laboratory, Wolfson Building, Parks Road, OX1 3QD, England
pp. 94-99

Dynamic verification of Multicore Communication applications in MCAPI (PDF)

Subodh Sharma , School of Computing, University of Utah, Salt Lake City, 84112, USA
Ganesh Gopalakrishnan , School of Computing, University of Utah, Salt Lake City, 84112, USA
Eric Mercer , Computer Science Department, Brigham Young University, Provo, UT 84602, USA
pp. 100-105

Airwolf-TG: A test generator for assertion-based dynamic verification (PDF)

Jason G. Tong , Integrated Microsystems Laboratory - McGill University, Montréal, Québec, Canada
Marc Boule , Integrated Microsystems Laboratory - McGill University, Montréal, Québec, Canada
Zeljko Zilic , Integrated Microsystems Laboratory - McGill University, Montréal, Québec, Canada
pp. 106-113

A versatile scheme for the validation, testing and debugging of High Speed Serial Interfaces (PDF)

Yongquan Fan , Department of ECE, McGill University, Canada
Zeljko Zilic , Department of ECE, McGill University, Canada
pp. 114-121

Experience with widening based equivalence checking in realistic multimedia systems (PDF)

Sven Verdoolaege , Dept. of Computer Science, Katholieke Universiteit Leuven, Belgium
Martin Palkovic , IMEC, Leuven, Belgium
Maurice Bruynooghe , Dept. of Computer Science, Katholieke Universiteit Leuven, Belgium
Gerda Janssens , Dept. of Computer Science, Katholieke Universiteit Leuven, Belgium
Francky Catthoor , IMEC, Leuven, Belgium
pp. 122-129

A coordinated reachability analysis method for modular verification of asynchronous designs (PDF)

Hao Zheng , CSE dept. of the Univ. of South Florida, Tampa, 33620, USA
pp. 130-137

Modular arithmetic decision procedure with auto-correction mechanism (PDF)

Bijan Alizadeh , VLSI Design and Education Center (VDEC), University of Tokyo and CREST, Japan
Masahiro Fujita , VLSI Design and Education Center (VDEC), University of Tokyo and CREST, Japan
pp. 138-145

Activity-based refinement for abstraction-guided simulation (PDF)

Debapriya Chatterjee , Department of Computer Science and Engineering, University of Michigan, USA
Valeria Bertacco , Department of Computer Science and Engineering, University of Michigan, USA
pp. 146-153

IFRA: Post-silicon bug localization in processors (PDF)

Sung-Boem Park , Departments of Electrical Engineering and Computer Science, Stanford University, CA, USA
Subhasish Mitra , Departments of Electrical Engineering and Computer Science, Stanford University, CA, USA
pp. 154-159

RTL DFT techniques to enhance defect coverage for functional test sequences (PDF)

Hongxia Fang , ECE Dept., Duke University, Durham, NC, USA
Krishnendu Chakrabarty , ECE Dept., Duke University, Durham, NC, USA
Hideo Fujiwara , Nara Institute of Science and Technology, Japan
pp. 160-165

Hardware Trojan: Threats and emerging solutions (PDF)

Rajat Subhra Chakraborty , Dept. of Electrical Engineering and Computer Science, Case Western Reserve University, Cleveland, Ohio, USA
Seetharam Narasimhan , Dept. of Electrical Engineering and Computer Science, Case Western Reserve University, Cleveland, Ohio, USA
Swarup Bhunia , Dept. of Electrical Engineering and Computer Science, Case Western Reserve University, Cleveland, Ohio, USA
pp. 166-171

Design-for-debug for post-silicon validation: Can high-level descriptions help? (PDF)

Nicola Nicolici , Department of Electrical and Computer Engineering, McMaster University, Hamilton, ON L8S 4K1, Canada
Ho Fai Ko , Department of Electrical and Computer Engineering, McMaster University, Hamilton, ON L8S 4K1, Canada
pp. 172-175
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