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2008 IEEE International High Level Design Validation and Test Workshop (2008)
Incline Village, NV USA
Nov. 19, 2008 to Nov. 21, 2008
ISSN: 1552-6674
ISBN: 978-1-4244-2922-6
TABLE OF CONTENTS

Positioning test-benches and test-programs in interaction-oriented system-on-chip verification (PDF)

Xiaoxi Xu , School of Electrical and Electronic Engineering, the University of Adelaide, SA, 5005, Australia
Cheng-Chew Lim , School of Electrical and Electronic Engineering, the University of Adelaide, SA, 5005, Australia
Michael Liebelt , School of Electrical and Electronic Engineering, the University of Adelaide, SA, 5005, Australia
pp. 3-10

A method for hunting bugs that occur due to system conflicts (PDF)

Daniel Geist , Intel Israel, Haifa, Israel
Oded Vaida , Intel Israel, Haifa, Israel
pp. 11-17

Session 2: Test (PDF)

pp. 23-24

Test slice difference technique for low power encoding (PDF)

Wei-Lin Li , Department of Electrical Engineering, Tamkang University, 151, Ying-Chuan Rd. Tamsui, Taipei Hsien 251, Taiwan, R.O.C
Tsung-Tang Chen , Department of Electrical Engineering, Tamkang University, 151, Ying-Chuan Rd. Tamsui, Taipei Hsien 251, Taiwan, R.O.C
Po-Han Wu , Department of Electrical Engineering, Tamkang University, 151, Ying-Chuan Rd. Tamsui, Taipei Hsien 251, Taiwan, R.O.C
Jiann-Chyi Rau , Department of Electrical Engineering, Tamkang University, 151, Ying-Chuan Rd. Tamsui, Taipei Hsien 251, Taiwan, R.O.C
pp. 25-32

Panel: Software practices for verification/testbench management (PDF)

Shireesh Verma , Conexant Systems Inc, USA
Srinath Atluri , Cisco Systems Inc, USA
Valeria Bertacco , University of Michigan Ann Arbor, USA
Mark Glasser , Mentor Graphics Inc, USA
Badri Gopalan , Synopsys Inc, USA
Sharon Rosenberg , Cadence Systems Inc, USA
pp. 35-37

On dynamic switching of navigation for semi-formal design validation (PDF)

Ankur Parikh , Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, 24061 USA
Michael S. Hsiao , Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, 24061 USA
pp. 41-48

Multi-level Bounded Model Checking to detect bugs beyond the bound (PDF)

Tasuku Nishihara , Dept. of Electronics Engineering, The University of Tokyo, Japan 113-8656
Takeshi Matsumoto , VLSI Design and Education Center, The University of Tokyo, Japan 113-0032
Masahiro Fujita , VLSI Design and Education Center, The University of Tokyo, Japan 113-0032
pp. 49-55

Proving and disproving assertion rewrite rules with automated theorem provers (PDF)

Katell Morin-Allory , TIMA Laboratory, 46 avenue Félix Viallet 38031 Grenoble Cedex, France
Marc Boule , McGill University, 3480 University Street, Montreal, Quebec, Canada
Dominique Borrione , TIMA Laboratory, 46 avenue Félix Viallet 38031 Grenoble Cedex, France
Zeljko Zilic , McGill University, 3480 University Street, Montreal, Quebec, Canada
pp. 56-63

Janus: A novel use of Formal Verification for targeted behavioral equivalence (PDF)

Prakash Math , Intel Corporation, Hillsboro, Oregon, 97124 USA
David Hoenig , Intel Corporation, Hillsboro, Oregon, 97124 USA
pp. 64-70

Test and validation of a non-deterministic system — True Random Number Generator (PDF)

Kapila Udawatta , Intel Corporation, USA
Mehdi Ehsanian , Intel Corporation, USA
Sergey Maidanov , Intel Corporation, USA
Surya Musunuri , Intel Corporation, USA
pp. 77-84

Functional testing approaches for “BIFST-able” tlm_fifo (PDF)

H. Alemzadeh , CAD Research Laboratory, Department of Electrical and Computer Engineering, School of Engineering, University of Tehran, Iran
Z. Navabi , CAD Research Laboratory, Department of Electrical and Computer Engineering, School of Engineering, University of Tehran, Iran
S. Di Carlo , Contro and Computer Engineering Department, Politecnico di Torino, Italy
A. Scionti , Contro and Computer Engineering Department, Politecnico di Torino, Italy
P. Prinetto , Contro and Computer Engineering Department, Politecnico di Torino, Italy
pp. 85-92

IBM system z functional and performance verification using X-Gen (PDF)

Torsten Schober , IBM Germany Research & Development Lab, Germany
Bodo Hoppe , IBM Germany Research & Development Lab, Germany
Shimon Landa , IBM Research Laboratory in Haifa, Israel
Ronny Morad , IBM Research Laboratory in Haifa, Israel
pp. 93-100

Timing verification of distributed network systems at higher levels of abstraction (PDF)

Hassan Hatefi-Ardakani , Department of Computer Engineering, Sharif University of Technology, Tehran, Iran
Amir Masoud Gharehbaghi , Department of Computer Engineering, Sharif University of Technology, Tehran, Iran
Shaahin Hessabi , Department of Computer Engineering, Sharif University of Technology, Tehran, Iran
pp. 101-107

Session 7: Simulation (PDF)

pp. 108-110

Temporal parallel gate-level timing simulation (PDF)

Dusung Kim , University of Massachusetts, Dept. of Electrical & Computer Engineering, Amherst, 01003, USA
Maciej Ciesielski , University of Massachusetts, Dept. of Electrical & Computer Engineering, Amherst, 01003, USA
Kyuho Shim , Pusan National University, Department of Computer Engineering, Busan, Korea
Seiyang Yang , Pusan National University, Department of Computer Engineering, Busan, Korea
pp. 111-116

The role of parallel simulation in functional verification (PDF)

Giuseppe Di Guglielmo , Department of Computer Science, University of Verona, Italy
Franco Fummi , Department of Computer Science, University of Verona, Italy
Mark Hampton , Certess Moirans, France
Graziano Pravadelli , Department of Computer Science, University of Verona, Italy
Francesco Stefanni , Department of Computer Science, University of Verona, Italy
pp. 117-124

A HW/SW co-simulation framework for the verification of multi-CPU systems (PDF)

S. Cordibella , University of Verona - Department of Computer Science, Italy
F. Fummi , University of Verona - Department of Computer Science, Italy
G. Perbellini , University of Verona - Department of Computer Science, Italy
D. Quaglia , University of Verona - Department of Computer Science, Italy
pp. 125-131

Panel: SoC power management implications on validation and testing (PDF)

Bhanu Kapoor , Mimasic, USA
John Goodenough , ARM, USA
Shankar Hemmady , Synopsys, USA
Shireesh Verma , Conexant, USA
Manuel A. d'Abreu , Sandisk, USA
Kaushik Roy , Purdue University, USA
pp. 135-137

Special session - What’s so intelligent about testbenches? (PDF)

Avi Ziv , IBM, USA
Chris Wilson , IBM, USA
Adnan Hamid , Breker Verification, USA
Joerg Grosse , Certess, USA
pp. 141-142

Optimized coverage-directed random simulation (PDF)

I. Ugarte , Microelectronic Engineering Group. TEISA Dept. ETSIIT, University of Cantabria. Santander, Spain
P. Sanchez , Microelectronic Engineering Group. TEISA Dept. ETSIIT, University of Cantabria. Santander, Spain
pp. 145-152

Evaluation of an efficient control-oriented coverage metric (PDF)

Kiran Ramineni , Center for Embedded Computer Systems, University of California, Irvine 92697, USA
Shireesh Verma , Center for Embedded Computer Systems, University of California, Irvine 92697, USA
Ian G. Harris , Center for Embedded Computer Systems, University of California, Irvine 92697, USA
pp. 153-157

High-level vulnerability over space and time to insidious soft errors (PDF)

Kenneth M. Zick , Advanced Computer Architecture Laboratory, University of Michigan, Ann Arbor, 48109 USA
John P. Hayes , Advanced Computer Architecture Laboratory, University of Michigan, Ann Arbor, 48109 USA
pp. 161-168

Automating defects simulation and fault modeling for SRAMs (PDF)

Stefano Di Carlo , Politecnico di Torino, Control and Computer Engineering Department, Italy
Paolo Prinetto , Politecnico di Torino, Control and Computer Engineering Department, Italy
Alberto Scionti , Politecnico di Torino, Control and Computer Engineering Department, Italy
Zaid Al-Ars , Delft University of Technology, The Netherlands
pp. 169-176

Injecting intermittent faults for the dependability validation of commercial microcontrollers (PDF)

D. Gil , Grupo de Sistemas Tolerantes a Fallos (GSTF) - Instituto ITACA, Universidad Politécnica de Valencia, Spain
L.J. Saiz , Grupo de Sistemas Tolerantes a Fallos (GSTF) - Instituto ITACA, Universidad Politécnica de Valencia, Spain
J. Gracia , Grupo de Sistemas Tolerantes a Fallos (GSTF) - Instituto ITACA, Universidad Politécnica de Valencia, Spain
J.C. Baraza , Grupo de Sistemas Tolerantes a Fallos (GSTF) - Instituto ITACA, Universidad Politécnica de Valencia, Spain
P.J. Gil , Grupo de Sistemas Tolerantes a Fallos (GSTF) - Instituto ITACA, Universidad Politécnica de Valencia, Spain
pp. 177-184
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