The Community for Technology Leaders
2012 IEEE International High Level Design Validation and Test Workshop (HLDVT) (2007)
Irvine, CA, USA
Nov. 7, 2007 to Nov. 9, 2007
ISBN: 978-1-4244-1480-2
TABLE OF CONTENTS
Papers

Table of contents (Abstract)

pp. v-viii

Proceedings (Abstract)

pp. i-iv

Keynote (Abstract)

pp. ix-x

Reliable network-on-chip based on generalized de Bruijn graph (Abstract)

Mohammad Reza Kakoee , University of Tehran, Iran
Dhiraj K. Pradhan , University of Bristol, UK
Mohammad Hosseinabady , University of Bristol, UK
Jimson Mathew , University of Bristol, UK
pp. 3-10

Framework for fast and accurate performance simulation of multiprocessor systems (Abstract)

Eric Cheung , Department of Computer Science and Engineering, University of California Riverside, Riverside, 92521, USA
Harry Hsieh , Department of Computer Science and Engineering, University of California Riverside, Riverside, 92521, USA
Felice Balarin , Cadence Design Systems, Berkeley, California 95134, USA
pp. 21-28

Automatic TLM generation for C-Based MPSoC design (Abstract)

Samar Abdi , Center for Embedded Computer Systems, UC Irvine, CA 92697, USA
Lucky Lo Chi Yu Lo , Center for Embedded Computer Systems, UC Irvine, CA 92697, USA
pp. 29-36

Automatic buffer sizing for rate-constrained KPN applications on multiprocessor system-on-chip (Abstract)

Felice Balarin , Cadence Design Systems, Berkeley, California 95134, USA
Harry Hsieh , Department of Computer Science and Engineering, University of California Riverside, Riverside, 92521, USA
Eric Cheung , Department of Computer Science and Engineering, University of California Riverside, Riverside, 92521, USA
pp. 37-44

Post-silicon verification methodology on Sun (Abstract)

Catherine Ahlschlager , Sun Microsystems, Microelectronics Group, 4210 Network Circle, MS USCA21-114, Santa Clara, CA 95054, USA
Peter Isberg , Sun Microsystems, Microelectronics Group, 4210 Network Circle, MS USCA21-114, Santa Clara, CA 95054, USA
Jai Kumar , Sun Microsystems, Microelectronics Group, 4210 Network Circle, MS USCA21-114, Santa Clara, CA 95054, USA
pp. 47

Challenges in post-silicon verification of IBM (Abstract)

Shakti Kapoor , IBM Austin, TX, USA
pp. 48-52

Intel (Abstract)

Mauri Robert , Intel Corporation, 2088 Center Drive, MS 301, DuPont, WA 98327, USA
Bojan Tommy , Intel Corporation, Intel Development Center, M.T.M. Scientific Industries Center, Haifa 31015, Israel
Frumkin Igor , Intel Corporation, Intel Development Center, M.T.M. Scientific Industries Center, Haifa 31015, Israel
pp. 53-56

Session 4: Debug (Abstract)

pp. 57-58

Bug analysis and corresponding error models in real designs (Abstract)

Yang Zhao , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100080, China
Huawei Li , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100080, China
Xiaowei Li , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100080, China
Tong Xu , Microprocessor Center, Dept. of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100080, China
Tao Lv , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100080, China
pp. 59-64

Automatic error diagnosis and correction for RTL designs (Abstract)

Kai-hui Chang , EECS Department, University of Michigan, 48109-2121, USA
Igor L. Markov , EECS Department, University of Michigan, 48109-2121, USA
Ilya Wagner , EECS Department, University of Michigan, 48109-2121, USA
Valeria Bertacco , EECS Department, University of Michigan, 48109-2121, USA
pp. 65-72

Bridging RTL and gate: correlating different levels of abstraction for design debugging (Abstract)

Eric Cheung , University of California, 92521, USA
Harry Hsieh , University of California, 92521, USA
Xi Chen , Novas Software, Inc. San Jose, California 95110, USA
Yu-Chin Hsu , Novas Software, Inc. San Jose, California 95110, USA
Furshing Tsai , Novas Software, Inc. San Jose, California 95110, USA
pp. 73-80

Session 5: Test generation (Abstract)

pp. 81-82

Model-driven test generation for system level validation (Abstract)

Sumit Ahuja , CESCA, Virginia Tech, Blacksburg, VA 24061, USA
Ajit Dingankar , Validation Technology, Intel Corporation, Folsom, CA 95630, USA
Sandeep Shukla , CESCA, Virginia Tech, Blacksburg, VA 24061, USA
Deepak A. Mathaikutty , CESCA, Virginia Tech, Blacksburg, VA 24061, USA
pp. 83-90

Towards RTL test generation from SystemC TLM specifications (Abstract)

Mingsong Chen , Computer and Information Science and Engineering University of Florida, Gainesville, FL 32611, USA
Dhrubajyoti Kalita , Intel Corporation 1900 Prairie City Road, Folsom, CA 95630, USA
Prabhat Mishra , Computer and Information Science and Engineering University of Florida, Gainesville, FL 32611, USA
pp. 91-96

A novel formal approach to generate high-level test vectors without ILP and SAT solvers (Abstract)

Masahiro Fujita , VLSI Design and Education Center (VDEC), University of Tokyo, Japan
Bijan Alizadeh , VLSI Design and Education Center (VDEC), University of Tokyo, Japan
pp. 97-104

Hierarchical cache coherence protocol verification one level at a time through assume guarantee (Abstract)

Ching-Tsun Chou , Intel Corporation Santa Clara, CA 95054, USA
Yu Yang , Ganesh Gopalakrishnan School of Computing, University of Utah Salt Lake City, 84112, USA
Xiaofang Chen , Ganesh Gopalakrishnan School of Computing, University of Utah Salt Lake City, 84112, USA
Michael Delisi , Ganesh Gopalakrishnan School of Computing, University of Utah Salt Lake City, 84112, USA
pp. 107-114

Formal model construction using HDL simulation semantics (Abstract)

Dong Wang , Synopsys Inc. Advanced Technology Group, Japan
Joseph Buck , Synopsys Inc. Advanced Technology Group, Japan
Yunshan Zhu , Independent Consultant, Japan
pp. 115-122

An approach for computing the initial state for retimed synchronous sequential circuits (Abstract)

Wayne Wolf , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA
Noureddine Chabini , Department of Electrical and Computer Engineering, Royal Military College of Canada, USA
pp. 123-130

FFT Compiler: from math to efficient hardware HLDVT invited short paper (Abstract)

Markus Puschel , Electrical and Computer Engineering Department, Carnegie Mellon University, Pittsburgh, PA, U.S.A.
James C. Hoe , Electrical and Computer Engineering Department, Carnegie Mellon University, Pittsburgh, PA, U.S.A.
Franz Franchetti , Electrical and Computer Engineering Department, Carnegie Mellon University, Pittsburgh, PA, U.S.A.
Peter A. Milder , Electrical and Computer Engineering Department, Carnegie Mellon University, Pittsburgh, PA, U.S.A.
pp. 137-139

Transactors for parallel hardware and software co-design (Abstract)

Krste Asanovic , Computer Science Division, University of California at Berkeley, USA
pp. 140-142

Functional coverage measurements and results in post-Silicon validation of Core (Abstract)

Tommy Bojan , Intel Corporation, Intel Development Center, M.T.M, Scientific Industries Center, Haifa 31015, Israel
Manuel Aguilar Arreola , Intel Corporation, Latin America Design Services, Israel
pp. 145-150

Coverage-directed test generation through automatic constraint extraction (Abstract)

Onur Guzey , Department of ECE, UC-Santa Barbara, USA
Li-C. Wang , Department of ECE, UC-Santa Barbara, USA
pp. 151-158

Automatic generation of functional coverage models from CTL (Abstract)

Shireesh Verma , Center for Embedded Computer Systems, Department of Computer Science, University of California, Irvine, CA 92697, USA
Ian G. Harris , Center for Embedded Computer Systems, Department of Computer Science, University of California, Irvine, CA 92697, USA
Kiran Ramineni , Center for Embedded Computer Systems, Department of Computer Science, University of California, Irvine, CA 92697, USA
pp. 159-164

Session 10: Embedded Systems (Abstract)

pp. 169-170

Automating the IEEE std. 1500 compliance verification for embedded cores (Abstract)

A. Benso , Politecnico di Torino, Dipartimento di Automatica e Informatica, Italy
A. Bosio , Laboratoire d
S. Di Carlo , Politecnico di Torino, Dipartimento di Automatica e Informatica, Italy
P. Prinetto , Politecnico di Torino, Dipartimento di Automatica e Informatica, Italy
pp. 171-178

Validating the dependability of embedded systems through fault injection by means of loadable kernel modules (Abstract)

Massimo Violante , Dipartimento di Automatica ed Informatica, Politecnico di Torino, Torino, Italy
Marco Murciano , Dipartimento di Automatica ed Informatica, Politecnico di Torino, Torino, Italy
pp. 179-186

AME: an abstract middleware environment for validating networked embedded systems applications (Abstract)

S. Vinco , University of Verona - Department of Computer Science - Strada le Grazie, 37134, Verona, Italy
F. Fummi , University of Verona - Department of Computer Science - Strada le Grazie, 37134, Verona, Italy
G. Perbellini , University of Verona - Department of Computer Science - Strada le Grazie, 37134, Verona, Italy
D. Quaglia , University of Verona - Department of Computer Science - Strada le Grazie, 37134, Verona, Italy
pp. 187-194

Author Index (Abstract)

pp. 195-196
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