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2012 IEEE International High Level Design Validation and Test Workshop (HLDVT) (2006)
Monterey, CA
Nov. 8, 2006 to Nov. 10, 2006
ISBN: 1-4244-0679-X
TABLE OF CONTENTS
Papers
Papers

Committees (PDF)

pp. iv

Table of Contents (PDF)

pp. v-viii
Papers

Test Directive Generation for Functional Coverage Closure Using Inductive Logic Programming (Abstract)

null Hsiou-Wen Hsueh , Dept. of Comput. Sci., Bristol Univ.
K. Eder , Dept. of Comput. Sci., Bristol Univ.
pp. 11-18

Automated Coverage Directed Test Generation Using a Cell-Based Genetic Algorithm (Abstract)

A. Samarah , Dept. of Electr.&Comput. Eng., Concordia Univ., Montreal, Que.
S. Tahar , Dept. of Electr.&Comput. Eng., Concordia Univ., Montreal, Que.
A. Habibi , Dept. of Electr.&Comput. Eng., Concordia Univ., Montreal, Que.
N. Kharma , Dept. of Electr.&Comput. Eng., Concordia Univ., Montreal, Que.
pp. 19-26

Trends in Test: Challenges and Techniques (Abstract)

W. Meyer , Synopsys, Inc, Mountain View, CA
pp. 37

Formal Verifications in Modern Chip Designs (Abstract)

null Kei-Yong Khoo , Cadence Design Syst., Inc., San Jose, CA
pp. 38

DFT and Probabilistic Testability Analysis at RTL (Abstract)

M.B. Santos , IST/INESC-ID, Lisboa
J.C. Teixeira , IST/INESC-ID, Lisboa
J.M. Fernandes , IST/INESC-ID, Lisboa
A.L. Oliveira , IST/INESC-ID, Lisboa
pp. 41-47

Easily Testable Implementation for Bit Parallel Multipliers in GF (2m) (Abstract)

H. Rahaman , Dept. of Comput. Sci., Bristol Univ.
J. Mathew , Dept. of Comput. Sci., Bristol Univ.
pp. 48-54

Error Detection Using Model Checking vs. Simulation (Abstract)

I.G. Harris , Dept. of Comput. Sci., California Univ., Irvine, CA
P. Lee , Dept. of Comput. Sci., California Univ., Irvine, CA
S. Verma , Dept. of Comput. Sci., California Univ., Irvine, CA
pp. 55-58

Assertion-based Verification of Behavioral Descriptions with Non-linear Solver (Abstract)

I. Ugarte , TEISA Dept. ETSIIT, Cantabria Univ., Santander
P. Sanchez , TEISA Dept. ETSIIT, Cantabria Univ., Santander
pp. 61-68

Efficient Automata-Based Assertion-Checker Synthesis of PSL Properties (Abstract)

M. Boule , McGill Univ., Montreal, Que.
Z. Zilic , McGill Univ., Montreal, Que.
pp. 69-76

Specification Language for Transaction Level Assertions (Abstract)

T. Steininger , Infineon Technol. AG, Munich
W. Ecker , Infineon Technol. AG, Munich
V. Esen , Infineon Technol. AG, Munich
M. Velten , Infineon Technol. AG, Munich
M. Hull , Infineon Technol. AG, Munich
pp. 77-84

On the Automatic Transactor Generation for TLM-based Design Flows (Abstract)

F. Fummi , Dipt. di Informatica, Universita di Verona
N. Bombieri , Dipt. di Informatica, Universita di Verona
pp. 85-92

Addressing Test Generation Challenges for Configurable Processor Verification (Abstract)

M. Vinov , IBM Res. Lab. in Haifa
I. Jaeger , IBM Res. Lab. in Haifa
A. Adir , IBM Res. Lab. in Haifa
Y. Lichtenstein , IBM Res. Lab. in Haifa
M. Rimon , IBM Res. Lab. in Haifa
pp. 95-101

DeepTrans - Extending the Model-based Approach to Functional Verification of Address Translation Mechanisms (Abstract)

A. Koyfman , IBM Res. Lab., Haifa
L. Founder , IBM Res. Lab., Haifa
A. Adir , IBM Res. Lab., Haifa
Y. Katz , IBM Res. Lab., Haifa
pp. 102-110

CP with Architectural State Lookup for Functional Test Generation (Abstract)

B. Gutkovich , Intel Corp., Haifa
A. Moss , Intel Corp., Haifa
pp. 111-118

Reusable On-Chip System Level Verification for Simulation Emulation and Silicon (Abstract)

O. Ben-Moshe , Freescale Semicond. Israel, Herzelia
A. Maman , Freescale Semicond. Israel, Herzelia
R. Slater , Freescale Semicond. Israel, Herzelia
H. Miller , Freescale Semicond. Israel, Herzelia
N. Levi , Freescale Semicond. Israel, Herzelia
S. Goldschlager , Freescale Semicond. Israel, Herzelia
D. Bell , Freescale Semicond. Israel, Herzelia
H. Gilboa , Freescale Semicond. Israel, Herzelia
pp. 119-126

Transaction Routing and its Verification by Correct Model Transformations (Abstract)

D. Gajski , Center for Embedded Comput. Syst., California Univ., Irvine, CA
S. Abdi , Center for Embedded Comput. Syst., California Univ., Irvine, CA
pp. 129-136

Taming the Complexity of STE-based Design Verification Using Program Slicing (Abstract)

V.M. Vedula , Design&Technol. Solutions, Intel Corp., Austin, TX
pp. 137-142

Distance-Guided Hybrid Verification with GUIDO (Abstract)

V. Bertacco , Dept. of Electr. Eng.&Comput. Sci., Michigan Univ., Ann Arbor, MI
pp. 151

EverLost: A Flexible Platform for Industrial-Strength Abstraction-Guided Simulation (Abstract)

Alan Hu , Department of Computer Science, University of British Columbia, Vancouver
pp. 151-152

Semi-Formal Verification at IBM (Abstract)

J.R. Baumgartner , IBM Syst.&Technol. Group, Austin, TX
pp. 152

Guiding CNF-SAT Search by Analyzing Constraint-Variable Dependencies and Clause Lengths (Abstract)

V. Durairaj , Dept. of Electr.&Comput. Eng., Utah Univ., Salt Lake, UT
P. Kalla , Dept. of Electr.&Comput. Eng., Utah Univ., Salt Lake, UT
pp. 155-161

Equivalence Checking with Rule-Based Equivalence Propagation and High-Level Synthesis (Abstract)

T. Nishihara , Dept. of Electron. Eng., Tokyo Univ.
T. Matsumoto , Dept. of Electron. Eng., Tokyo Univ.
pp. 162-169

IChecker: An Efficient Checker for Inductive Invariants (Abstract)

null Feng Lu , Dept. of ECE, California Univ., Santa Barbara, CA
K.-T. Cheng , Dept. of ECE, California Univ., Santa Barbara, CA
pp. 176-180

Panel: Assertion-Based Verification -What's the Big Deal? (Abstract)

Sandeep Shukla , Virginia Tech., Blacksburg, Virginia 24061. Email: shukla@vt.edu
Carl Pixley , Synopsys
Pranav Ashar , Real Intent
Avner Landver , Cadence
Harry Foster , Mentor Graphics
Jacob Abrahams , UT Austin
Alan Hu , University of British Columbia, Vancouver, Canada. Email: ajh@cs.ubc.ca
pp. 183

Runtime Deadlock Analysis of SystemC Designs (Abstract)

null Vi Pham , Dept. of Comput. Sci., Univ. of California Riverside, CA
H. Hsieh , Dept. of Comput. Sci., Univ. of California Riverside, CA
E. Cheung , Dept. of Comput. Sci., Univ. of California Riverside, CA
P. Satapathy , Dept. of Comput. Sci., Univ. of California Riverside, CA
pp. 187-194

Extracting a simplified view of design functionality via vector simulation (Abstract)

L.-C. Wang , Dept. of Electr.&Comput. Eng., California Univ., Santa Barbara, CA
C. Wen , Dept. of Electr.&Comput. Eng., California Univ., Santa Barbara, CA
O. Guzey , Dept. of Electr.&Comput. Eng., California Univ., Santa Barbara, CA
pp. 195-202

Polychronous Methodology For System Design: A True Concurrency Approach (Abstract)

D. Mathaikutty , FERMAT Lab., Virginia Tech, Blacksburg, VA
S. Shukla , FERMAT Lab., Virginia Tech, Blacksburg, VA
S. Suhaib , FERMAT Lab., Virginia Tech, Blacksburg, VA
pp. 211-214

Author Index (Abstract)

pp. 215
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