The Community for Technology Leaders
2012 IEEE International High Level Design Validation and Test Workshop (HLDVT) (2005)
Napa Valley, CA, USA
Nov. 30, 2005 to Dec. 2, 2005
ISBN: 0-7803-9571-9
TABLE OF CONTENTS

Simulation-based functional test generation for embedded processors (Abstract)

Kwang-Ting Cheng , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
L.C. Wang , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
C.H.-P. Wen , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 3-10

Table of contents (Abstract)

pp. v-viii

Scalable defect mapping and configuration of memory-based nanofabrics (Abstract)

G. de Veciana , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
M.F. Jacome , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
Chen He , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 11-18

Improvement of fault injection techniques based on VHDL code modification (Abstract)

J. Gracia , Dept. of Comput. Eng., Valencia Tech. Univ., Spain
J.C. Baraza , Dept. of Comput. Eng., Valencia Tech. Univ., Spain
P.J. Gil , Dept. of Comput. Eng., Valencia Tech. Univ., Spain
D. Gil , Dept. of Comput. Eng., Valencia Tech. Univ., Spain
pp. 19-26

Establishing latch correspondence for embedded circuits of PowerPC microprocessors (Abstract)

A. Sen , Dept. of Comput. Eng., Valencia Tech. Univ., Spain
J. Bhadra , Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA
H. Anand , Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA
M.S. Abadir , Dept. of Comput. Eng., Valencia Tech. Univ., Spain
pp. 37-44

Sequential equivalence checking based on k-th invariants and circuit SAT solving (Abstract)

Feng Lu , Dept. of ECE, Univ. of California at Santa Barbara, CA, USA
K.-T. Cheng , Dept. of ECE, Univ. of California at Santa Barbara, CA, USA
pp. 45-51

VERISEC: verifying equivalence of sequential circuits using SAT (PDF)

M. Syal , Bradley Dept. of Electr. & Comput. Eng., Virginia Tech, Blacksburg, VA, USA
M.S. Hsiao , Bradley Dept. of Electr. & Comput. Eng., Virginia Tech, Blacksburg, VA, USA
pp. 52-59

Automated clock inference for stream function-based system level specifications (PDF)

S.K. Shukla , Bradley Dept. of Electr. & Comput. Eng., Virginia Tech, Blacksburg, VA, USA
J.-P. Talpin , INRIA-IRISA, Rennes, France
pp. 63-70

Cosimulation of ITRON-based embedded software with SystemC (PDF)

S. Chikada , Graduate Sch. of Inf. Sci., Nagoya Univ., Japan
S. Honda , Bradley Dept. of Electr. & Comput. Eng., Virginia Tech, Blacksburg, VA, USA
H. Takada , Dept. of Comput. Eng., Valencia Tech. Univ., Spain
H. Tomiyama , Dept. of Comput. Eng., Valencia Tech. Univ., Spain
pp. 71-76

A software test program generator for verifying system-on-chips (Abstract)

A. Parashkevov , Dept. of Comput. Eng., Valencia Tech. Univ., Spain
A. Cheng , Sch. of Electr. & Electron. Eng., Adelaide Univ., SA, Australia
Cheng-Chew Lim , Sch. of Electr. & Electron. Eng., Adelaide Univ., SA, Australia
pp. 79-86

Stimulus generation for interface protocol verification using the nondeterministic extended finite state machine model (Abstract)

Jing-Yang Jou , Dept. of Electron. Eng., National Chiao Tung Univ., Hsinchu, Taiwan
Che-Hua Shih , Dept. of Electron. Eng., National Chiao Tung Univ., Hsinchu, Taiwan
Juinn-Dar Huang , Dept. of Electron. Eng., National Chiao Tung Univ., Hsinchu, Taiwan
pp. 87-93

DVGen: a test generator for the transmeta Efficeon VLIW processor (Abstract)

S.G. Govindaraju , Transmeta Corp., Santa Clara, CA, USA
K.D. Rich , Transmeta Corp., Santa Clara, CA, USA
D. Dobrikin , Transmeta Corp., Santa Clara, CA, USA
R. Shaw , Transmeta Corp., Santa Clara, CA, USA
pp. 94-101

Copyright page (Abstract)

pp. ii

Committees (Abstract)

pp. iv

Reuse in system-level stimuli-generation (Abstract)

Y. Katz , IBM Res. Lab, Haifa, Israel
I. Jaeger , IBM Res. Lab, Haifa, Israel
Y. Lichtenstein , IBM Res. Lab, Haifa, Israel
R. Emek , IBM Res. Lab, Haifa, Israel
pp. 105-111

Harnessing machine learning to improve the success rate of stimuli generation (Abstract)

S. Fine , IBM Res. Lab., Haifa, Israel
A. Ziv , IBM Res. Lab., Haifa, Israel
Y. Naveh , IBM Res. Lab., Haifa, Israel
I. Jaeger , IBM Res. Lab., Haifa, Israel
A. Freund , IBM Res. Lab., Haifa, Israel
pp. 112-118

A new simulation-based property checking algorithm based on partitioned alternative search space traversal (PDF)

M.S. Hsiao , Dept. of Electr. & Comput. Eng., Virginia Tech, Blacksburg, VA, USA
Qingwei Wu , Dept. of Electr. & Comput. Eng., Virginia Tech, Blacksburg, VA, USA
pp. 121-126

Validating families of latency insensitive protocols (PDF)

S. Suhaib , FERMAT Lab, Virginia Tech, Blacksburg, VA, USA
D. Berner , IBM Res. Lab., Haifa, Israel
D. Mathaikutty , FERMAT Lab, Virginia Tech, Blacksburg, VA, USA
S. Shukla , FERMAT Lab, Virginia Tech, Blacksburg, VA, USA
pp. 127-134

GASIM: a fast Galois field based simulator for functional model (PDF)

T.L. Rajaprabhu , FERMAT Lab, Virginia Tech, Blacksburg, VA, USA
D.K. Pradhan , Dept. of Comput. Sci., Bristol Univ., UK
A.K. Singh , FERMAT Lab, Virginia Tech, Blacksburg, VA, USA
A.M. Jabir , IBM Res. Lab., Haifa, Israel
pp. 135-142

Overlap reduction in symbolic system traversal (Abstract)

T. Kropf , Dept. of Comput. Eng., Tubingen Univ., Germany
P.K. Nalla , Dept. of Comput. Eng., Tubingen Univ., Germany
J. Ruf , Dept. of Comput. Eng., Tubingen Univ., Germany
W. Rosenstiel , Dept. of Comput. Eng., Tubingen Univ., Germany
P.M. Peranandam , Dept. of Comput. Eng., Tubingen Univ., Germany
R.J. Weiss , Dept. of Comput. Eng., Tubingen Univ., Germany
pp. 145-152

Formal verification of high-level conformance with symbolic simulation (Abstract)

A. Naik , Intel Corp., Hillsboro, OR, USA
R. Kaivola , Intel Corp., Hillsboro, OR, USA
pp. 153-159

A method for generation of GSTE assertion graphs (Abstract)

E. Smith , Comput. Lab., Oxford Univ., UK
pp. 160-167

Automatic abstraction refinement for Petri nets verification (Abstract)

Conghua Zhou , Dept. of Math., Nanjing Univ., China
Zhenyu Chen , Dept. of Math., Nanjing Univ., China
Decheng Ding , Dept. of Math., Nanjing Univ., China
pp. 168-174

An optimum algorithm for compacting error traces for efficient functional debugging (Abstract)

Jing-Yang Jou , Dept. of Electron. Eng., National Chiao-Tung Univ., Hsinchu, Taiwan
Chia-Chih Yen , Dept. of Electron. Eng., National Chiao-Tung Univ., Hsinchu, Taiwan
pp. 177-183

Increasing the deducibility in CNF instances for efficient SAT-based bounded model checking (PDF)

V.C. Vimjam , Dept. of Electr. & Comput. Eng.,, Virginia Tech, Blacksburg, VA, USA
M.S. Hsiao , Dept. of Electr. & Comput. Eng.,, Virginia Tech, Blacksburg, VA, USA
pp. 184-191

B-cubing theory: new possibilities for efficient SAT-solving (Abstract)

D. Babic , Dept. of Comput. Sci., British Columbia Univ., Vancouver, BC, Canada
J. Bingham , Dept. of Comput. Sci., British Columbia Univ., Vancouver, BC, Canada
A.J. Hu , Dept. of Comput. Sci., British Columbia Univ., Vancouver, BC, Canada
pp. 192-199

Multilevel design validation in a secure embedded system (Abstract)

P. Schaumont , Dept. of Comput. Eng., Tubingen Univ., Germany
D.D. Hwang , Dept. of Elec. Eng., UCLA, Los Angeles, CA, USA
Shenglin Yang , Dept. of Elec. Eng., UCLA, Los Angeles, CA, USA
I. Verbauwhede , Dept. of Elec. Eng., UCLA, Los Angeles, CA, USA
pp. 203-210

Security evaluation against electromagnetic analysis at design time (Abstract)

S. Moore , Comput. Lab., Cambridge Univ., UK
A.T. Markettos , Comput. Lab., Cambridge Univ., UK
Huiyun Li , Comput. Lab., Cambridge Univ., UK
pp. 211-218

Formal meaning of coverage metrics in simulation-based hardware design verification (Abstract)

I. Ugarte , Dept. of TEISA, Cantabria Univ., Santander, Spain
P. Sanchez , Dept. of TEISA, Cantabria Univ., Santander, Spain
pp. 221-228

Advanced analysis techniques for cross-product coverage (Abstract)

H. Azatchi , IBM Res. Lab. in Haifa, Israel
K. Zohar , IBM Res. Lab. in Haifa, Israel
A. Ziv , IBM Res. Lab. in Haifa, Israel
L. Fournier , IBM Res. Lab. in Haifa, Israel
pp. 229-236

A proof of correctness for the construction of property monitors (Abstract)

D. Borrione , Tima Lab., Grenoble, France
K. Morin-Allory , Tima Lab., Grenoble, France
pp. 237-244

Functional coverage - is your design exposed? (Abstract)

A. Ziv , Tima Lab., Grenoble, France
A. Piziali , Tima Lab., Grenoble, France
pp. 247

Author index (Abstract)

pp. 249-250

Chairs' welcome message (Abstract)

pp. iii
83 ms
(Ver )