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2012 IEEE International High Level Design Validation and Test Workshop (HLDVT) (2004)
Sonoma Valley, CA, USA
Nov. 10, 2004 to Nov. 12, 2004
ISBN: 0-7803-8714-7
TABLE OF CONTENTS

Committees (PDF)

pp. iv
Session 1: Formal Techniques

Enhancing sequential depth computation with a branch-and-bound algorithm (Abstract)

Chia-Chih Yen , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Jing-Yang Jou , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
pp. 3-8

Reference model based RTL verification: an integrated approach (Abstract)

W.N.N. Hung , Synplicity Inc., Sunnyvale, CA, USA
N. Narasimhan , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
pp. 9-13

Table of contents (Abstract)

pp. v-viii

Dynamic guiding of bounded property checking (Abstract)

T. Kropf , Dept. of Comput. Eng., Tubingen Univ., Germany
P.M. Peranandam , Dept. of Comput. Eng., Tubingen Univ., Germany
W. Rosenstiel , Dept. of Comput. Eng., Tubingen Univ., Germany
R.J. Weiss , Dept. of Comput. Eng., Tubingen Univ., Germany
J. Ruf , Dept. of Comput. Eng., Tubingen Univ., Germany
pp. 15-18

Towards an efficient assertion based verification of SystemC designs (Abstract)

A. Habibi , Concordia Univ., Montreal, Que., Canada
S. Tahar , Concordia Univ., Montreal, Que., Canada
pp. 19-22
Session 2: Processor-oriented Validation

Instruction level test methodology for CPU core software-based self-testing (Abstract)

S. Shamshiri , Electr. & Comput. Eng. Dept., Tehran Univ., Iran
H. Esmaeilzadeh , Electr. & Comput. Eng. Dept., Tehran Univ., Iran
Z. Navabi , Electr. & Comput. Eng. Dept., Tehran Univ., Iran
pp. 25-29

Simplifying design and verification for structural hazards and datapaths in pipelined circuits (Abstract)

M.D. Aagaard , Electr. & Comput. Eng. Dept., Tehran Univ., Iran
J.T. Higgins , Electr. & Comput. Eng. Dept., Tehran Univ., Iran
pp. 31-36

ATPG based functional test for data paths: application to a floating point unit (Abstract)

I. Bayraktaroglu , Design for Test Technol. Group, Sun MicroSystems Inc., Sunnyvale, CA, USA
M. d'Abreu , Electr. & Comput. Eng. Dept., Tehran Univ., Iran
pp. 37-40

Formal verification of pipelined processors with load-value prediction (Abstract)

M.N. Velev , Design for Test Technol. Group, Sun MicroSystems Inc., Sunnyvale, CA, USA
pp. 41-46
Session 3: Decision Diagrams for Verification

On using a 2-domain partitioned OBDD data structure in verification (Abstract)

K.-T. Cheng , Electr. & Comput. Eng. Dept., Tehran Univ., Iran
A.C.-C. Lin , Dept. of Comput. Eng., Tubingen Univ., Germany
L.-C. Wang , Electr. & Comput. Eng. Dept., Tehran Univ., Iran
T. Feng , Cadence Design Syst. Inc., San Jose, CA, USA
pp. 49-54

Variable ordering for taylor expansion diagrams (Abstract)

M. Ciesielski , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
D. Gomez-Prado , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
S. Askar , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
Q. Ren , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
E. Boutillon , Dept. of Comput. Eng., Tubingen Univ., Germany
pp. 55-59

MODD for CF: a representation for fast evaluation of multiple-output functions (Abstract)

D.K. Pradhan , Bristol Univ., UK
T.L. Rajaprabhu , Bristol Univ., UK
A.M. Jabir , Bristol Univ., UK
A.K. Singh , Bristol Univ., UK
pp. 61-66
Session 4: Validation Pattern Generation

Functional verification based on the EFSM model (Abstract)

C. Marconcini , Dipt. di Informatica, Univ. di Verona, Italy
F. Fummi , Dipt. di Informatica, Univ. di Verona, Italy
G. Pravadelli , Dipt. di Informatica, Univ. di Verona, Italy
pp. 69-74

Enhancing the efficiency of Bayesian network based coverage directed test generation (Abstract)

M. Braun , STZ Softwaretechnik, Esslingen, Germany
S. Fine , Dipt. di Informatica, Univ. di Verona, Italy
A. Ziv , Dipt. di Informatica, Univ. di Verona, Italy
pp. 75-80

Mutation-based validation of high-level microprocessor implementations (Abstract)

H. Al-Asaad , Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA
J. Campos , Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA
pp. 81-86
Session 5: Behavioral Modeling

Effects of property ordering in an incremental formal modeling methodology (Abstract)

Syed Suhaib , FERMAT Lab., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
Deepak Mathaikutty , FERMAT Lab., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
Sandeep Shukla , FERMAT Lab., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
pp. 89-94

Efficient test-based model generation for legacy reactive systems (Abstract)

T. Margaria , Gottingen Univ., Germany
H. Raffelt , FERMAT Lab., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
B. Steffen , Bristol Univ., UK
O. Niese , FERMAT Lab., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
pp. 95-100

Copyright (Abstract)

pp. ii

Model validation for mapping specification behaviors to processing elements (Abstract)

D. Gajski , Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
S. Abdi , Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
pp. 101-106
Session 6: Fault Coverage Analysis

Test quality for high level structural test (Abstract)

E.J. McCluskey , Center for Reliable Comput., Stanford Univ., CA, USA
A. AI- Yamani , Center for Reliable Comput., Stanford Univ., CA, USA
pp. 109-114

On code coverage measurement for Verilog-A (Abstract)

Mu-Shun Lee , Dept. of Electr. Eng., Nat. Central Univ., Chung-li, Taiwan
Mu-Shun Lee , Dept. of Electr. Eng., Nat. Central Univ., Chung-li, Taiwan
Yuan-Bin Sha , Dept. of Electr. Eng., Nat. Central Univ., Chung-li, Taiwan
pp. 115-120

On identifying functionally untestable transition faults (Abstract)

X. Liu , Texas Instrum. Inc., Dallas, TX, USA
M.S. Hsiao , Dept. of Electr. Eng., Nat. Central Univ., Chung-li, Taiwan
pp. 121-126
Session 7: SAT Solving Approaches

CNF formula simplification using implication reasoning (Abstract)

M.S. Hsiao , Dept. of Electr. Eng., Nat. Central Univ., Chung-li, Taiwan
Rajat Arora , Cadence Design Syst. Inc., San Jose, CA, USA
pp. 129-134

Dynamic analysis of constraint-variable dependencies to guide SAT diagnosis (Abstract)

P. Kalla , Dept. of Electr. & Comput; Eng., Utah Univ., Salt Lake City, UT, USA
V. Durairaj , Dept. of Electr. & Comput; Eng., Utah Univ., Salt Lake City, UT, USA
pp. 135-140

Exploiting hypergraph partitioning for efficient Boolean satisfiability (Abstract)

V. Duraira , Dept. of Electr. & Comput. Eng., Utah Univ., Salt Lake City, UT, USA
P. Kalla , Dept. of Electr. & Comput. Eng., Utah Univ., Salt Lake City, UT, USA
pp. 141-146
Session 8: Validation of Network Architectures

An event-based network-on-chip monitoring service (Abstract)

K. Goossens , Bristol Univ., UK
A. Radulescu , Dept. of Electr. Eng., Nat. Central Univ., Chung-li, Taiwan
T. Basten , Eindhoven Univ. of Technol., Netherlands
J. Meerbergen , Dept. of Comput. Eng., Tubingen Univ., Germany
C. Ciordas , Eindhoven Univ. of Technol., Netherlands
pp. 149-154

Assertion-based power/performance analysis of network processor architectures (Abstract)

J. Yang , California Univ., Riverside, CA, USA
W. Wu , California Univ., Riverside, CA, USA
J. Yu , California Univ., Riverside, CA, USA
X. Chen , California Univ., Riverside, CA, USA
H. Hsieh , California Univ., Riverside, CA, USA
pp. 155-160

Validation of the dependability of CAN-based networked systems (Abstract)

J. Perez , California Univ., Riverside, CA, USA
M. Violante , California Univ., Riverside, CA, USA
M. Ramasso , California Univ., Riverside, CA, USA
M. Reorda , California Univ., Riverside, CA, USA
F. Corno , Dip. Automatica e Informatica, Politecnico di Torino, Italy
pp. 161-164
Session 9: High-level Validation

High level hardware validation using hierarchical message sequence charts (Abstract)

K. Takayama , California Univ., Riverside, CA, USA
P.K. Murthy , Fujitsu Labs. of America, Sunnyvale, CA, USA
S.R. Rajan , California Univ., Riverside, CA, USA
pp. 167-172

Analysis of the influence of processor hidden registers on the accuracy of fault injection techniques (Abstract)

J. Gracia , Fault Tolerant Syst. Group, Polytech. Univ. of Valencia, Spain
D. Gil , Fault Tolerant Syst. Group, Polytech. Univ. of Valencia, Spain
P.J. Gil , Fault Tolerant Syst. Group, Polytech. Univ. of Valencia, Spain
J.C. Baraza , Fault Tolerant Syst. Group, Polytech. Univ. of Valencia, Spain
pp. 173-178

On equivalence checking between behavioral and RTL descriptions (Abstract)

M. Fujita , VLSI Design & Educ. Center, Tokyo Univ., Japan
pp. 179-184
Session 10: Panel - "Driving the Intelligent Testbench: Are we there yet?"

Driving the intelligent testbanch: are we there yet? (Abstract)

H.D. Foster , VLSI Design & Educ. Center, Tokyo Univ., Japan
pp. 188

What happened to the intelligent test bench? (Abstract)

G. Smith , VLSI Design & Educ. Center, Tokyo Univ., Japan
pp. 189

Author Index (Abstract)

pp. 191

Back cover (Abstract)

pp. 194

Chairs' welcome message (Abstract)

A.J. Hu , VLSI Design & Educ. Center, Tokyo Univ., Japan
I.G. Harris , Fault Tolerant Syst. Group, Polytech. Univ. of Valencia, Spain
pp. iii
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