The Community for Technology Leaders
2012 IEEE International High Level Design Validation and Test Workshop (HLDVT) (2003)
San Francisco, CA, USA
Nov. 12, 2003 to Nov. 14, 2003
ISBN: 0-7803-8236-6
TABLE OF CONTENTS
Hldvt

Software-based self-test methodology for crosstalk faults in processors (Abstract)

Li Chen , Dept. of Electr. & Comput. Eng., Univ. of California, San Diego, CA, USA
Xiaoliang Bai , Dept. of Electr. & Comput. Eng., Univ. of California, San Diego, CA, USA
S. Dey , Dept. of Electr. & Comput. Eng., Univ. of California, San Diego, CA, USA
pp. 11-16

FPgen - a test generation framework for datapath floating-point verification (Abstract)

R. Nagel , IBM Haifa Res. Labs., Israel
M. Aharoni , IBM Haifa Res. Labs., Israel
A. Koifman , IBM Haifa Res. Labs., Israel
S. Asaf , IBM Haifa Res. Labs., Israel
L. Fournier , IBM Haifa Res. Labs., Israel
pp. 17-22

Piparazzi: a test program generator for micro-architecture flow verification (Abstract)

O. Peled , IBM Res. Lab., Haifa, Israel
E. Bin , IBM Res. Lab., Haifa, Israel
A. Adir , IBM Res. Lab., Haifa, Israel
A. Ziv , IBM Res. Lab., Haifa, Israel
pp. 23-28

Automatic functional verification of memory oriented global source code transformations (Abstract)

M. Bruynooghe , IBM Res. Lab., Haifa, Israel
G. Janssens , IBM Res. Lab., Haifa, Israel
K.C. Shashidhar , IMEC, Heverlee, Belgium
F. Catthoor , IBM Res. Lab., Haifa, Israel
pp. 31-36

Refactoring digital hardware designs with assertion libraries (Abstract)

J. Tompkins , IBM Haifa Res. Labs., Israel
H. Foster , IBM Res. Lab., Haifa, Israel
F.M. De Paula , IBM Res. Lab., Haifa, Israel
J.A. Nacif , IBM Res. Lab., Haifa, Israel
F.M. De Paula , Mindspeed Technol. Inc., USA
pp. 37-42

High-level optimization of pipeline design (Abstract)

J.P.L. Campbell , Sch. of Comp. Sci., Waterloo Univ., Ont., Canada
N.A. Day , IBM Res. Lab., Haifa, Israel
pp. 43-48

Integrating CNF and BDD based SAT solvers (Abstract)

S. Gopalakrishnan , Dept. of Electr. & Comput. Eng., Utah Univ., Salt Lake City, UT, USA
V. Durairaj , Dept. of Electr. & Comput. Eng., Utah Univ., Salt Lake City, UT, USA
P. Kalla , Dept. of Electr. & Comput. Eng., Utah Univ., Salt Lake City, UT, USA
pp. 51-56

Enhancing SAT-based equivalence checking with static logic implications (PDF)

M.S. Hsiao , Virginia Tech, Blacksburg, VA, USA
R. Arora , Virginia Tech, Blacksburg, VA, USA
pp. 63-68

Relating vehicle-level and network-level reliability through high-level fault injection (PDF)

P. Gabrielli , Virginia Tech, Blacksburg, VA, USA
S. Tosato , Dept. of Electr. & Comput. Eng., Utah Univ., Salt Lake City, UT, USA
F. Corno , Dipt. di Automatica e Informatica, Politecnico di Torino, Italy
pp. 71-76

Testing ThumbPod: Softcore bugs are hard to find (Abstract)

A. Hodjat , Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
K. Sakiyama , Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
Y. Fan , Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
S. Yang , Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
P. Schaumont , Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
B. Lai , Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
I. Verbauwhede , Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
D. Hwang , Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
pp. 77-82

Verifying LOC based functional and performance constraints (Abstract)

Xi Chen , California Univ., Riverside, CA, USA
F. Balarin , Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
H. Hsieh , California Univ., Riverside, CA, USA
Y. Watanabe , Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
pp. 83-88

Comparison of Bayesian networks and data mining for coverage directed verification category simulation-based verification (Abstract)

M. Braun , STZ Softwaretechnik, Esslingen, Germany
W. Rosenstiel , California Univ., Riverside, CA, USA
K.-D. Schubert , Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
pp. 91-95

Enhancing the control and efficiency of the covering process [logic verification] (Abstract)

A. Ziv , IBM Res. Lab in Haifa, Haifa Univ. Campus, Israel
S. Fine , IBM Res. Lab in Haifa, Haifa Univ. Campus, Israel
pp. 96-101

Functional vector generation for assertion-based verification at behavioral level using interval analysis (Abstract)

P. Sanchez , Cantabria Univ., Santander, Spain
I. Ugarte , Cantabria Univ., Santander, Spain
pp. 102-107

Redundant functional faults reduction by saboteurs synthesis [logic verification] (Abstract)

G. Pravadelli , Dipt. di Inf., Verona Univ., Italy
C. Marconcini , Dipt. di Inf., Verona Univ., Italy
F. Fummi , Dipt. di Inf., Verona Univ., Italy
pp. 108-113

ATPG-based preimage computation: efficient search space pruning with ZBDD (PDF)

M.S. Hsiao , Virginia Tech, Blacksburg, VA, USA
K. Chandrasekar , Virginia Tech, Blacksburg, VA, USA
pp. 117-122

BDD-based verification of scalable designs (Abstract)

R. Drechsler , Inst. of Comput. Sci., Bremen Univ., Germany
D. Grosse , Inst. of Comput. Sci., Bremen Univ., Germany
pp. 123-128

Matching in the presence of don't cares and redundant sequential elements for sequential equivalence checking (Abstract)

B. Rouzeyre , Inst. of Comput. Sci., Bremen Univ., Germany
S. Rahim , LIRMM - Synplicity, Montpellier, France
L. Torres , Dipt. di Inf., Verona Univ., Italy
J. Rampon , Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
pp. 129-134

Mathematical framework for representing discrete functions as word-level polynomials (Abstract)

D.K. Pradhan , Dept. of Comput. Sci., Bristol Univ., UK
M. Ciesielski , Dipt. di Inf., Verona Univ., Italy
S. Askar , Inst. of Comput. Sci., Bremen Univ., Germany
pp. 135-139

High-level test generation for hardware testing and software validation (Abstract)

M. Sonza Reorda , Politecnico di Torino, Italy
O. Goloubeva , Politecnico di Torino, Italy
M. Violante , Politecnico di Torino, Italy
pp. 143-148

Scheduling of transactions for system-level test-case generation (Abstract)

Y. Naveh , IBM Haifa Res. Lab., Israel
R. Emek , IBM Haifa Res. Lab., Israel
pp. 149-154

A comparison of BDDs, BMC, and sequential SAT for model checking (Abstract)

G. Parthasarathy , California Univ., Santa Barbara, CA, USA
M.K. Iyer , California Univ., Santa Barbara, CA, USA
K.-T. Cheng , California Univ., Santa Barbara, CA, USA
pp. 157-162

Genetic algorithms: the philosopher's stone or an effective solution for high-level TPG? (Abstract)

A. Fin , Dipt. di Inf., Verona Univ., Italy
F. Fummi , Dipt. di Inf., Verona Univ., Italy
pp. 163-168

A method for the evaluation of behavioral fault models (Abstract)

M. Moussa , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
I.G. Harris , California Univ., Santa Barbara, CA, USA
E. Gaudette , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
pp. 169-172

What's the next 'big thing' in simulation-based verification? (Abstract)

Y. Kas , Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
B. Bailey , California Univ., Santa Barbara, CA, USA
M. Levinger , Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
A. Ziv , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
B. Joyner , Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
J. Abraham , California Univ., Santa Barbara, CA, USA
pp. 175

Author index (PDF)

pp. 177-178
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