The Community for Technology Leaders
2012 IEEE International High Level Design Validation and Test Workshop (HLDVT) (2002)
Cannes, France
Oct. 27, 2002 to Oct. 29, 2002
ISBN: 0-7803-7655-2
TABLE OF CONTENTS
Hldvt

VHDL-based simulation environment for Proteo NoC (Abstract)

J. Nurmi , IDCS, Tampere Univ. of Technol., Finland
D. Siguenza-Tortosa , IDCS, Tampere Univ. of Technol., Finland
pp. 1-6

Slightly-off-specification failures in the time-triggered architecture (Abstract)

A. Ademaj , Real-Time Syst. Group, Vienna Univ. of Technol., Austria
pp. 7-12

High-level design verification using Taylor Expansion Diagrams: first results (Abstract)

P. Kalla , Utah Univ., Salt Lake City, UT, USA
M. Ciesielski , IDCS, Tampere Univ. of Technol., Finland
pp. 13-17

A 1000X speed up for properties completeness evaluation (Abstract)

A. Fedeli , STMicroelectronics, Brianza, Italy
A. Castelnuovo , STMicroelectronics, Brianza, Italy
pp. 18-22

Checking temporal properties in SystemC specifications (Abstract)

A. Braun , Tubingen Univ., Germany
J. Gerlach , Tubingen Univ., Germany
W. Rosenstiel , Tubingen Univ., Germany
pp. 23-27

High level validation of next-generation microprocessors (Abstract)

B. Bentley , Intel Corp., Hillsboro, OR, USA
pp. 31-35

Top-level validation of system-on-chip in Esterel Studio (Abstract)

J. Dormoy , Esterel Technol., Villeneuve-Loubet, France
A. Bouali , Esterel Technol., Villeneuve-Loubet, France
L. Blanc , Esterel Technol., Villeneuve-Loubet, France
G. Berry , Esterel Technol., Villeneuve-Loubet, France
pp. 36-41

Formal analysis and validation of continuous-time Markov chain based system level power management strategies (Abstract)

G. Norman , Sch. of Comput. Sci., Univ. of Birmingham, UK
D. Parker , Sch. of Comput. Sci., Univ. of Birmingham, UK
S.K. Shukla , Esterel Technol., Villeneuve-Loubet, France
M. Kwiatkowska , Sch. of Comput. Sci., Univ. of Birmingham, UK
pp. 45-50

Timed HW-SW cosimulation using native execution of OS and application SW (Abstract)

A.A. Jerraya , TIMA Lab., SLS Group, Grenoble, France
Sungjoo Yoo , TIMA Lab., SLS Group, Grenoble, France
M. Bacivarov , TIMA Lab., SLS Group, Grenoble, France
pp. 51-56

Setting break-points in distributed time-triggered architecture (Abstract)

I. Smaili , TTTech Computertechnik AG, Vienna, Austria
A. Ademaj , TIMA Lab., SLS Group, Grenoble, France
pp. 57-62

A hierarchical approach for designing dependable systems (Abstract)

N. Mazzoca , TIMA Lab., SLS Group, Grenoble, France
S. Venticinque , Esterel Technol., Villeneuve-Loubet, France
M. Sonza Reorda , Dipt. di Automatica e Informatica, Politecnico di Torino, Italy
M. Violante , Dipt. di Automatica e Informatica, Politecnico di Torino, Italy
pp. 63-68

Using Aspect-GAMMA in the design of embedded systems (Abstract)

M. Reniers , Eindhoven Univ. of Technol., Netherlands
G. Russello , Eindhoven Univ. of Technol., Netherlands
T. Basten , Eindhoven Univ. of Technol., Netherlands
M. Mousavi , Eindhoven Univ. of Technol., Netherlands
M. Chaudron , Eindhoven Univ. of Technol., Netherlands
pp. 69-74

Generating concurrent test-programs with collisions for multi-processor verification (Abstract)

G. Shurek , IBM Res. Lab., Haifa, Israel
A. Adir , IBM Res. Lab., Haifa, Israel
pp. 77-82

Breaking an application specific instruction-set processor: the first step towards embedded software testing (Abstract)

B.L. Otero Mathijssen , IBM Res. Lab., Haifa, Israel
J.A. Huisken , IBM Res. Lab., Haifa, Israel
J.T.M.H. Dielissen , IBM Res. Lab., Haifa, Israel
pp. 89-92

An effective and flexible approach to functional verification of processor families (Abstract)

D. Malandain , STMicroelectronics, Rousset, France
Y. Arbetman , Eindhoven Univ. of Technol., Netherlands
P. Palmen , IBM Res. Lab., Haifa, Israel
M. Taylor , IBM Res. Lab., Haifa, Israel
M. Aharoni , Eindhoven Univ. of Technol., Netherlands
pp. 93-98

Automatic functional test program generation for pipelined processors using model checking (Abstract)

N. Dutt , Architectures & Compilers for Embedded Syst. (ACES), California Univ., Irvine, CA, USA
P. Mishra , Architectures & Compilers for Embedded Syst. (ACES), California Univ., Irvine, CA, USA
pp. 99-103

Accelerated verification of RTL assertions based on satisfiability solvers (Abstract)

S. Ikram , Architectures & Compilers for Embedded Syst. (ACES), California Univ., Irvine, CA, USA
A. Mokkedem , Eindhoven Univ. of Technol., Netherlands
R. Fraer , Logic & Validation Technol., Intel Corp., Haifa, Israel
T. Leonard , Eindhoven Univ. of Technol., Netherlands
G. Kamhi , IBM Res. Lab., Haifa, Israel
pp. 107-110

Alignability equivalence of synchronous sequential circuits (Abstract)

A. Rosenmann , Dept. of Logic & Validation Technol., Intel, Haifa, Israel
Z. Hanna , Dept. of Logic & Validation Technol., Intel, Haifa, Israel
pp. 111-114

TRANS: efficient sequential verification of loop-free circuits (Abstract)

Z. Hanna , IBM Res. Lab., Haifa, Israel
Z. Khasidashvili , Design Technol. Div., Intel, Haifa, Israel
J. Moondanos , Dept. of Logic & Validation Technol., Intel, Haifa, Israel
pp. 115-120

Verification of a DSP IP cores by model checking (Abstract)

M. Sarlotte , Eindhoven Univ. of Technol., Netherlands
P. Koumou , Dept. of Logic & Validation Technol., Intel, Haifa, Israel
C. Antoine , Eindhoven Univ. of Technol., Netherlands
H.N. Nguyen , Design Technol. Div., Intel, Haifa, Israel
B. Candaele , IBM Res. Lab., Haifa, Israel
pp. 121-124

Formal verification of embedded system designs at multiple levels of abstraction (Abstract)

Fang Chen , California Univ., Riverside, CA, USA
F. Balarin , Eindhoven Univ. of Technol., Netherlands
Xi Chen , California Univ., Riverside, CA, USA
Y. Watanabe , Eindhoven Univ. of Technol., Netherlands
H. Hsieh , California Univ., Riverside, CA, USA
pp. 125-130

Prototyping of embedded digital systems from SDL language: a case study (Abstract)

F.G. Moraes , Eindhoven Univ. of Technol., Netherlands
L.H.L. Ries , Eindhoven Univ. of Technol., Netherlands
C.A.M. Marcon , California Univ., Riverside, CA, USA
F. Hessel , California Univ., Riverside, CA, USA
A.M. Amory , California Univ., Riverside, CA, USA
pp. 133-138

An equivalence checking methodology for hardware oriented C-based specifications (Abstract)

T. Ogawa , California Univ., Riverside, CA, USA
T. Sakunkonchak , California Univ., Riverside, CA, USA
H. Saito , Res. Center for Adv. Sci. & Technol., Univ. of Tokyo, Japan
T. Nanya , Eindhoven Univ. of Technol., Netherlands
M. Fujita , Eindhoven Univ. of Technol., Netherlands
pp. 139-144

X-Gen: a random test-case generator for systems and SoCs (Abstract)

G. Bergman , Res. Lab., IBM Corp., Haifa, Israel
M. Farkash , Res. Lab., IBM Corp., Haifa, Israel
A. Goldin , Res. Lab., IBM Corp., Haifa, Israel
Y. Katz , Res. Lab., IBM Corp., Haifa, Israel
Y. Naveh , Res. Lab., IBM Corp., Haifa, Israel
I. Jaeger , Res. Lab., IBM Corp., Haifa, Israel
G. Aloni , Res. Lab., IBM Corp., Haifa, Israel
R. Emek , Res. Lab., IBM Corp., Haifa, Israel
I. Dozoretz , Res. Lab., IBM Corp., Haifa, Israel
pp. 145-150

Constructing reusable testbenches (Abstract)

B.J. Mohd , Synopsys Professional Services, Marlboro, MA, USA
A. Wakefield , Synopsys Professional Services, Marlboro, MA, USA
pp. 151-155

Taking the best out of two worlds: prototyping and hardware emulation (Abstract)

M. Munteanu , Philips Semicond., Zurich, Switzerland
M. Wannemacher , Philips Semicond., Zurich, Switzerland
S. Perret , Philips Semicond., Zurich, Switzerland
R. Singer , Philips Semicond., Zurich, Switzerland
pp. 156-161

A simple and effective compression scheme for test pins reduction (Abstract)

M.-L. Flottes , Lab. d'Informatique de Robotique, CNRS, Montpellier, France
B. Rouzeyre , Lab. d'Informatique de Robotique, CNRS, Montpellier, France
R. Poirier , Lab. d'Informatique de Robotique, CNRS, Montpellier, France
pp. 165-168

High-level and hierarchical test sequence generation (Abstract)

M. Violante , Res. Lab., IBM Corp., Haifa, Israel
Z. Peng , Embedded Syst. Lab., Linkoping Univ., Sweden
O. Goloubeva , Lab. d'Informatique de Robotique, CNRS, Montpellier, France
G. Jervan , Embedded Syst. Lab., Linkoping Univ., Sweden
M.S. Reorda , Philips Semicond., Zurich, Switzerland
pp. 169-174

Test generation for hardware-software covalidation using non-linear programming (Abstract)

I.G. Harris , Massachusetts Univ., Amherst, MA, USA
Fei Xin , Massachusetts Univ., Amherst, MA, USA
pp. 175-180

Experimental validation of fault detection and fault tolerance mechanisms (Abstract)

J. Sosnowski , Inst. of Comput. Sci., Warsaw Univ. of Technol., Poland
P. Gawkowski , Inst. of Comput. Sci., Warsaw Univ. of Technol., Poland
pp. 181-186

Author Index (PDF)

pp. 187-188
112 ms
(Ver 3.1 (10032016))