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Sixth IEEE International High-Level Design Validation and Test Workshop (2001)
Monterey, California
Dec. 7, 2001 to Dec. 9, 2001
ISBN: 0-7695-1411-1
TABLE OF CONTENTS
Session 1: Design Validation of Microprocessors

Relating Buffer-Oriented Microarchitecture Validation to High-Level Pipeline Functionality (Abstract)

Noppanunt Utamaphethai , Carnegie Mellon University
R.D. (Shawn) Blanton , Carnegie Mellon University
John Paul Shen , Carnegie Mellon University
pp. 3

Automatic Validation of Pipeline Specifications (Abstract)

Prabhat Mishra , University of California, Irvine
Nikil Dutt , University of California, Irvine
Alex Nicolau , University of California, Irvine
pp. 9
Session 2: Techniques for High Level Design Validation and Test
Session 3: Invited Session: State-of-the-Art Formal Verification Techniques

Symbolic Simulation Techniques - State-of-the-art and Applications (Abstract)

Claudia Blank , Darmstadt University of Technology
Hans Eveking , Darmstadt University of Technology
Jens Levihn , Darmstadt University of Technology
Gerd Ritter , Darmstadt University of Technology
pp. 45
Session 4: Short Papers: High Level Verification and Analysis

RTL Functional Verification Using Excitation and Observation Coverage (Abstract)

Byeong Min , Texas A&M University
Gwan Choi , Texas A&M University
pp. 58

Taylor Expansion Diagrams: a New Representation for RTL Verification (Abstract)

M. Ciesielski , University of Massachusetts
P. Kalla , University of Massachusetts
Z. Zeng , University of Massachusetts
B. Rouzeyre , LIRMM
pp. 70
Session 5: Short papers: High Level Timing Verification and Testing

Fast Timed Cosimulation of HW/SW Implementation of Embedded Multiprocessor SoC Communication (Abstract)

Sungjoo Yoo , SLS group, TIMA/INPG
Gabriela Nicolescu , SLS group, TIMA/INPG
Lovic Gauthier , SLS group, TIMA/INPG
Ahmed A. Jerraya , SLS group, TIMA/INPG
pp. 79

Test Pattern Generation for Timing-Induced Functional Errors in Hardware-Software Systems (Abstract)

Srikanth Arekapudi , University of Massachusetts
Fei Xin , University of Massachusetts
Jinzheng Peng , University of Massachusetts
Ian G. Harris , University of Massachusetts
pp. 83

Combining Complex Event Models and Timing Constraints (Abstract)

Marek Jersak , Technical University of Braunschweig
Kai Richter , Technical University of Braunschweig
Rolf Ernst , Technical University of Braunschweig
pp. 89
Session 6: Verification of Real Life Designs

Proving Sequential Consistency by Model Checking (Abstract)

Tim Braun , Technical University of Darmstadt
Kai S. Juse , Technical University of Darmstadt
Anne Condon , Univ. of British Columbia
Alan J. Hu , Univ. of British Columbia
Marius Laza , Univ. of British Columbia
Michael Leslie , Univ. of British Columbia
Rita Sharma , Univ. of British Columbia
pp. 103

Formal Verification of the Pentium 4 Multiplier (Abstract)

Roope Kaivola , Intel Corporation
Naren Narasimhan , Intel Corporation
pp. 115
Session 7: High-Level Specification and Verification

Constraints Specification at Higher Levels of Abstraction (Abstract)

Felice Balarin , Cadence Berkeley Laboratories
Jerry Burch , Cadence Berkeley Laboratories
Luciano Lavagno , Cadence Berkeley Laboratories
Yosinori Watanabe , Cadence Berkeley Laboratories
Roberto Passerone , University of California at Berkeley
Alberto Sangiovanni-Vincentelli , University of California at Berkeley
pp. 129
Session 8: High-Level Test Generation and Coverage Analysis

On Generation of The Minimum Pattern Set for Data Path Elements in SoC Design Verification Based on Port Order Fault Model (Abstract)

Chun-Yao Wang , National Chiao Tung University,
Shing-Wu Tung , National Chiao Tung University,
Jing-Yang Jou , National Chiao Tung University,
pp. 145

Observability Enhanced Coverage Analysis of C programs for Functional Validation (Abstract)

Farzan Fallah , Fujitsu Laboratories of America, Inc.
Indradeep Ghosh , Fujitsu Laboratories of America, Inc.
pp. 157
Session 9: Improved Techniques for Boolean Reasoning

Using Cutwidth to Improve Symbolic Simulation and Boolean Satisfiability (Abstract)

Dong Wang , Carnegie Mellon University
Edmund Clarke , Carnegie Mellon University
Yunshan Zhu , Synopsys Inc.
James Kukula , Synopsys Inc.
pp. 165

An Enhanced Cut-points Algorithm in Formal Equivalence Verification (Abstract)

Zurab Khasidashvili , Intel Architecture Group
John Moondanos , Intel Architecture Group
Daher Kaiss , Intel Architecture Group
Ziyad Hanna , Intel Architecture Group
pp. 171

An Analysis of ATPG and SAT algorithms for Formal Verification (Abstract)

G. Parthasarathy , Univ. of California, Santa Barbara
Kwang-Ting Cheng , Univ. of California, Santa Barbara
Chung-Yang Huang , Verplex Systems Inc
pp. 177

Author Index (PDF)

pp. 183
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