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2012 IEEE International High Level Design Validation and Test Workshop (HLDVT) (2000)
Berkeley, California
Nov. 8, 2000 to Nov. 10, 2000
ISBN: 0-7695-0786-7
TABLE OF CONTENTS

Welcoming Message (PDF)

pp. viii
Session 1: Advances in High-Level Test I: Chair: Kapila Udawatta, Intel

An RT-level fault model with high gate level correlation (Abstract)

F. Corno , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
G. Cumani , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
M. Sonza Reorda , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
G. Squillero , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
pp. 3

A novel methodology for hierarchical test generation using functional constraint composition (Abstract)

V.M. Vedula , Center for Comput. Eng. Res., Texas Univ., Austin, TX, USA
J.A. Abraham , Center for Comput. Eng. Res., Texas Univ., Austin, TX, USA
pp. 9

Use of constraint solving in order to generate test vectors for behavioral validation (Abstract)

M.L. Nivet , CNRS, Corsica Univ., Corte, France
C. Paoli , CNRS, Corsica Univ., Corte, France
J.F. Santucci , CNRS, Corsica Univ., Corte, France
pp. 15

Behavioral-level test vector generation for system-on-chip designs (Abstract)

M.S. Reorda , NEC USA C&C Res. Lab., USA
M. Rebaudengo , NEC USA C&C Res. Lab., USA
L. Lavagno , NEC USA C&C Res. Lab., USA
M. Lajolo , NEC USA C&C Res. Lab., USA
M. Violante , NEC USA C&C Res. Lab., USA
pp. 21
Session 2: Validation and Test for Microprocessor Designs: Chair: Magdy Abadir, Motorola

An approach to functional testing of VLIW architectures (Abstract)

F. Ferrandi , Politecnico di Milano, Italy
D. Sciuto , Politecnico di Milano, Italy
M. Beardo , Politecnico di Milano, Italy
F. Bruschi , Politecnico di Milano, Italy
pp. 29

A new method for on-line state machine observation for embedded microprocessors (Abstract)

C. Galke , CE Res. Group, Tech. Univ. Cottbus, Germany
H.T. Vierhaus , CE Res. Group, Tech. Univ. Cottbus, Germany
M. Pflanz , CE Res. Group, Tech. Univ. Cottbus, Germany
pp. 34

Verification of in-order execution in pipelined processors (Abstract)

H. Tomiyama , Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
N. Dutt , Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
T. Yoshino , Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
pp. 40
Session 3: Hardware/Software Co-Validation: Chair: Abhijit Ghosh, Synopsys

Silicon debug of a co-processor array for video applications (Abstract)

G.J. van Rootselaar , Philips Res. Lab., Eindhoven, Netherlands
B. Vermeulen , Philips Res. Lab., Eindhoven, Netherlands
pp. 47

Interface based hardware/software validation of a system-on-chip (Abstract)

S. Dey , Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA, USA
D. Panigrahi , Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA, USA
C.N. Taylor , Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA, USA
pp. 53

Hardware/software co-debugging for reconfigurable computing (Abstract)

A. Tiwari , Dept. of Electr. & Comput. Eng., Cincinnati Univ., OH, USA
K.A. Tomko , Dept. of Electr. & Comput. Eng., Cincinnati Univ., OH, USA
pp. 59

Functional verification of an embedded network component by co-simulation with a real network (Abstract)

P. Schaumont , IMEC, Leuven, Belgium
R. Pasko , IMEC, Leuven, Belgium
R. Cmar , IMEC, Leuven, Belgium
S. Vernalde , IMEC, Leuven, Belgium
pp. 64
Session 4: Formal Verification Techniques and Applications: Chair: Masahiro Fujita, University of Tokyo

Compositional verification of an ATM switch module using interface recognizer/suppliers (IRS) (Abstract)

E. Cerny , Dept. d'Inf. et de Recherche Oper., Montreal Univ., Que., Canada
M.S. Jahanpour , Dept. d'Inf. et de Recherche Oper., Montreal Univ., Que., Canada
pp. 71

An approach to high-level synthesis system validation using formally verified transformations (Abstract)

R. Vermuri , Cincinnati Univ., OH, USA
R. Radhakrishnan , Cincinnati Univ., OH, USA
E. Teica , Cincinnati Univ., OH, USA
pp. 80
Session 5: Issues in High-Level Design Validation: Chair: Timothy Kam

On statistical behavior of branch coverage in testing behavioral VHDL models (Abstract)

T. Chen , Dept. of Electr. Eng., Colorado State Univ., Fort Collins, CO, USA
A. Hajjar , Dept. of Electr. Eng., Colorado State Univ., Fort Collins, CO, USA
A. von Mayrhauser , Dept. of Electr. Eng., Colorado State Univ., Fort Collins, CO, USA
pp. 89

Variable size analysis and validation of computation quality (Abstract)

F.N. Eko , Dept. of Comput. Sci. & Commun. Eng., Kyushu Univ., Fukuoka, Japan
H. Yasnura , Dept. of Comput. Sci. & Commun. Eng., Kyushu Univ., Fukuoka, Japan
Cao Yun , Dept. of Comput. Sci. & Commun. Eng., Kyushu Univ., Fukuoka, Japan
H. Yamashita , Dept. of Comput. Sci. & Commun. Eng., Kyushu Univ., Fukuoka, Japan
pp. 95
Session 6:Advances in High-Level Test II: Chair: Irith Pomeranz, Purdue University

Formal operator testability methods for behavioral-level DFT using value ranges (Abstract)

S. Seshadri , Mentor Graphics Corp., Warren, NJ, USA
M.S. Hsiao , Mentor Graphics Corp., Warren, NJ, USA
pp. 105

System level testability analysis using Petri nets (Abstract)

Tianjing Jiang , Dept. of Electr. Eng., Virginia Univ., Charlottesville, VA, USA
J.H. Aylor , Dept. of Electr. Eng., Virginia Univ., Charlottesville, VA, USA
R.H. Klenke , Dept. of Electr. Eng., Virginia Univ., Charlottesville, VA, USA
Gang Han , Dept. of Electr. Eng., Virginia Univ., Charlottesville, VA, USA
pp. 112

High level fault simulation: experiments and results on ITC'99 benchmarks (Abstract)

D. Federici , CNRS, Corse Univ., France
P. Bisgambiglia , CNRS, Corse Univ., France
J.-F. Santucci , CNRS, Corse Univ., France
pp. 118

On choosing test criteria for behavioral level hardware design verification (Abstract)

T. Chen , Dept. of Comput. Sci., Colorado State Univ., Fort Collins, CO, USA
A. von Mayhauser , Dept. of Comput. Sci., Colorado State Univ., Fort Collins, CO, USA
A. Read , Dept. of Comput. Sci., Colorado State Univ., Fort Collins, CO, USA
C. Anderson , Dept. of Comput. Sci., Colorado State Univ., Fort Collins, CO, USA
J. Kok , Dept. of Comput. Sci., Colorado State Univ., Fort Collins, CO, USA
A. Haijar , Dept. of Comput. Sci., Colorado State Univ., Fort Collins, CO, USA
pp. 124
Session 7: Formal Verification Techniques: Chair: Tom Henzinger, UC Berkeley

Abstraction techniques for verification of multiple tightly coupled counters, registers and comparators (Abstract)

S.P. Levitan , Dept. of Electr. Eng., Pittsburgh Univ., PA, USA
Yee-Wing Hsieh , Dept. of Electr. Eng., Pittsburgh Univ., PA, USA
pp. 133

Refining abstract equivalence analysis for embedded system design (Abstract)

H. Hsieh , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
F. Balarin , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 139

Toward automated abstraction for protocols on branching networks (Abstract)

M. Jones , Sch. of Comput., Utah Univ., Salt Lake City, UT, USA
G. Gopalakrishnan , Sch. of Comput., Utah Univ., Salt Lake City, UT, USA
pp. 147
Session 8: Advances in Simulation-Based Verification: Chair: Alan Hu, University of British Columbia

Data flow based cache prediction using local simulation (Abstract)

F. Wolf , Inst. fur Datenverarbeitungsanlagen, Tech. Univ. Braunschweig, Germany
R. Ernst , Inst. fur Datenverarbeitungsanlagen, Tech. Univ. Braunschweig, Germany
pp. 155

Checking temporal properties under simulation of executable system descriptions (Abstract)

J. Ruf , Wilhelm-Schickard-Inst. fur Inf., Tubingen Univ., Germany
T. Kropf , Wilhelm-Schickard-Inst. fur Inf., Tubingen Univ., Germany
D.W. Hoffmann , Wilhelm-Schickard-Inst. fur Inf., Tubingen Univ., Germany
W. Rosenstiel , Wilhelm-Schickard-Inst. fur Inf., Tubingen Univ., Germany
pp. 161

Compilation-based software performance estimation for system level design (Abstract)

E. Harcourt , Cadence Design Syst. Inc., San Jose, CA, USA
L. Lavagno , Cadence Design Syst. Inc., San Jose, CA, USA
M. Lajolo , Cadence Design Syst. Inc., San Jose, CA, USA
M.T. Lazarescu , Cadence Design Syst. Inc., San Jose, CA, USA
J.R. Bammi , Cadence Design Syst. Inc., San Jose, CA, USA
pp. 167

Transformation of algorithmic simulation vector sets considering mapping problems of I/O operations (Abstract)

W. Rosenstiel , Forschungszentrum Inf., Karlsruhe Univ., Germany
C. Hansen , Forschungszentrum Inf., Karlsruhe Univ., Germany
pp. 173

Author Index (PDF)

pp. 179
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